BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a resistor and a manufacturing method thereof, and more particularly, to a resistor and a manufacturing method for a resistor integrated with a transistor having metal gate.
2. Description of the Prior Art
To increase the performance of transistors, metal gates are popularly used in the semiconductor field: the metal gates competent to the high dielectric constant (hereinafter abbreviated as high-K) gate dielectric layer replace the traditional polysilicon gates to be the control electrode. The metal gate approach can be categorized to the gate first process and the gate last process. And the gate last process gradually replaces the gate first process because it provides more material choices for the high-k gate dielectric layer and the metal gate.
Additionally, resistors are elements which are often used for providing regulated voltage and for filtering noise in a circuit. The resistors generally include polysilicon and silicide layers.
In the current semiconductor field, though the fabricating processes are improved with the aim of reaching high yields, it is found that integration of the manufacturing methods of those different kinds of semiconductor devices are very complicated and difficult. Therefore, a method for fabricating a resistor integrated with a transistor having metal gate is still in needed.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, a manufacturing method for a resistor integrated with a transistor having metal gate, is provided. The manufacturing method includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.
According to another aspect of the present invention, a resistor is provided. The resistor includes a substrate, a polysilicon portion positioned on the substrate, and two metal portions respectively positioned on two opposite ends of the polysilicon portion. The metal portions respectively comprise a U-shaped high-k gate dielectric layer in bottoms.
According to the manufacturing method for a resistor integrated with a transistor having metal gate provided by the present invention, the resistor and the transistor having the metal gate are integrated without increasing process complexity. Furthermore, since the resistor includes the metal portions, the materials contacted to the contacts are simplified and thus the material choice of the contacts is increased and the process window is improved. More important, since the resistor includes the metal portions which possess superior thermal stability, the stability and the performance of the resistor are both consequently improved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various Figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1-8 are schematic drawings illustrating a manufacturing method for a resistor integrated with a transistor having metal gate provided by a preferred embodiment of the present invention, wherein
FIG. 2 is a schematic drawing in a step subsequent to FIG. 1,
FIG. 3 is a schematic drawing in a step subsequent to FIG. 2,
FIG. 4 is a schematic drawing in a step subsequent to FIG. 3,
FIG. 5 is a schematic drawing in a step subsequent to FIG. 4,
FIG. 6 is a schematic drawing in a step subsequent to FIG. 5,
FIG. 7 is a schematic drawing in a step subsequent to FIG. 6, and
FIG. 8 is a schematic drawing in a step subsequent to FIG. 7.
DETAILED DESCRIPTION
Please refer to FIGS. 1-8, which are schematic drawings illustrating a manufacturing method for a resistor integrated with a transistor having metal gate provided by a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 100 having a transistor region 102 and a resistor region 104 defined thereon is provided. The substrate 100 also includes a plurality of shallow trench isolations (STIs) 106 positioned in between devices for providing electrical isolation. It is noteworthy that a STI 106 is formed in the resistor region 104. Then, a dielectric layer 107, a polysilicon layer 108, and a patterned hard mask 110 are sequentially formed on the substrate 100. The patterned hard mask 110 is formed to define a gate for a transistor and a resistor. It is noteworthy that the dielectric layer 107 formed between the substrate 100 and the polysilicon layer 108 can include conventional dielectric material such as silicon oxide.
Please refer to FIG. 2. Next, an etching process is performed to etch the polysilicon layer 108 and the dielectric layer 107 with the patterned hard mask 110 serving as an etching mask. Consequently, a dummy gate 112 is formed in the transistor region 102 and a resistor 114 is formed in the resistor region 104 simultaneously. Thereafter, lightly-doped drains (LDDs) 120 are formed in the substrate 100 respectively at two sides of the dummy gate 112. After forming the LDDs 120, a spacer 122 is formed on sidewalls of the dummy gate 112 and a spacer 124 is formed on sidewalls of the resistor 114. Subsequently, a source/drain 126 is formed in the substrate 100 respectively at two sides of the dummy gate 112, particularly at two sides of the spacer 122. Accordingly, a transistor 130 having the dummy gate 112 is obtained. Furthermore, a salicide 128 can be formed on surface of the source/drain 126 of the transistor 130. After forming the transistor 130 and the resistor 114, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed to cover the transistor 130 and the resistor 114. Since the steps and material choices for the abovementioned elements are well-known to those skilled in the art, those details are omitted herein in the interest of brevity. Furthermore, selective strain scheme (SSS) can be used in the preferred embodiment. For example, a selective epitaxial growth (SEG) method can be used to form the source/drain 126.
Please refer to FIG. 3. After forming the CESL 140 and the ILD layer 142, a planarization process is performed to remove a portion of the CESL 140, a portion of the ILD layer 142, and a portion of the patterned hard mask 110. Then an etching process, such as a dry etching process, is performed to remove the remnant patterned hard mask 110 and to expose the dummy gate 112 of the transistor 130 and the resistor 114. Then, a patterned hard mask 144 is formed on the substrate 100. The patterned hard mask 144 covers a portion of the resistor 114 and exposes two opposite ends of the resistor 114. Subsequently, a proper etching process is performed to remove the dummy gate 112 and portions of the resistor 114 not covered by the patterned hard mask 144. Thus a first trench 146 is formed in the transistor 130 and two the second trenches 148 are simultaneously formed in the two opposite ends of the resistor 114. It is noteworthy that because the preferred embodiment is integrated with the gate last process and the high-k last process, the dielectric layer 107 renders protection to the underneath substrate 100 during removing the dummy gate 112 of the transistor 130 and the portions of the resistor 114. The dielectric layer 107 therefore is exposed in the first trench 146 and the second trenches 148 after removing the dummy gate 112 and the portions of the resistor 114.
Please refer to FIG. 4. After forming the first trench 146 and the second trenches 148, the dielectric layer 107 exposed in the first trench and the second trenches 148 serves as an interfacial layer. Then the patterned hard mask 144 is removed and followed by sequentially forming a high-k gate dielectric layer 150 and a bottom barrier layer (not shown) on the substrate 100. The high-k gate dielectric layer 150 can be a metal oxide layer such as rare earth metal oxide. For example, the high-k gate dielectric layer 150 includes material selected from the group consisting of as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate, (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), and barium strontium titanate (BaxSr1-xTiO3, BST). The bottom barrier layer can include titanium nitride (TiN), but not limited to this. In addition, an etch stop layer (not shown) can be formed on the bottom barrier layer. The etch stop layer can include tantalum nitride (TaN), but not limited to this.
Please refer to FIG. 4 again. Next, a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) is performed to form a work function metal layer 152 in the first trench 146 and the second trenches 148. According to the preferred embodiment, the work function metal layer 152 can include suitable materials providing an appropriate work function for p-type transistor or n-type transistor. Therefore, the work function metal layer 152 has a work function, and the work function can be between 4.8 eV and 5.2 eV, or alternatively between 3.9 eV and 4.3 eV. Furthermore, the work function metal layer 152 can be a single-layered structure or a multilayered structure.
Please still refer to FIG. 4. Next, a blocking layer 154 is formed on the substrate 100. The blocking layer 154 can include photoresist, but not limited to this. The blocking layer 154 is formed in the first trench 146 and the second trenches 148. More important, a height of the blocking layer 154 is lower than a depth of the first trench 146 and of the second trenches 148. In other words, a surface of the blocking layer 154 is lower than an opening of the first trench 146 and of the second trenches 148.
Please refer to FIG. 5. Thereafter, an etching process is performed to remove the work function metal layer 152 and the high-k gate dielectric layer 150 not covered by the blocking layer 154 with any proper etchant. As shown in FIG. 5, the high-k gate dielectric layer 150 and the work function metal layer 152 respectively include a U shape after the etching process. And topmost portions of the U-shaped high-k gate dielectric layer 150 and of the U-shaped work function metal layer 152 are all lower than the openings of the first trench 146 and the second trenches. In other words, the high-k gate dielectric layer 150 and the work function metal layer 152 are remained only in the first trench 146 and the second trenches 148, particularly on the bottoms and sidewalls of the first trench 146 and of the second trenches 148. By performing the etching process, the high-k gate dielectric layer 150 is made not completely cover the sidewalls of the second trenches 148, therefore the electron transmission pathway are kept imperviously completed. Furthermore, since the overhangs composed of the high-k gate dielectric layer 150 and the work function metal layer 152 and formed on the openings of the first trench 146 are removed by the etching process, the gap-filling result of the following formed metal materials can be improved.
Please refer to FIG. 6. The blocking layer 154 is removed from the first trench 146 and the second trenches 148 and followed by forming a filling metal layer 156 on the work function metal layer 152 in the first trench 146 and the second trenches 148. Additionally, a top barrier layer (not shown) is preferably formed between the work function metal layer 152 and the filling metal layer 156. The top barrier layer can include TiN, but not limited to this. The filling metal layer 156 filling up the first trench 146 and the second trenches 148 includes materials with low resistance and superior gap-filling characteristic, such as aluminum (Al), titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but not limited to this.
Please refer to FIG. 7. Next, a planarization process such as a CMP process is performed to remove the unnecessary filling metal layer 156. Consequently, a metal gate 162 is formed and a transistor 130 having the metal gate 162 is obtained in the transistor region 102. More important, two metal structures 164 are respectively formed in the second trenches 148 in the resistor region 104 simultaneously with forming the metal gate 162. According to the preferred embodiment, the resistor 114 in the resistor region 104 is formed to have a polysilicon portion 108 and two metal portions 164. As shown in FIG. 7, the metal portions 164 of the resistor 114 are positioned respectively at the two opposite ends of the polysilicon portion 108. The metal portions 164 respectively have a U-shaped high-k gate dielectric layer 150 and a U-shaped work function metal layer 152 in bottoms, and topmost portions of the U-shaped high-k gate dielectric layer 150 and of the U-shaped work function metal layer 152 are lower than a surface of the metal portions 164. In addition, the ILD layer 142 and the CESL 140 can be selectively removed and sequentially reformed on the substrate 100 for improving performance of the transistor 130 in the preferred embodiment.
Please refer to FIG. 8. Then, a dielectric layer 170, preferably is a multilayered structure, is formed on the substrate 100. And a plurality of first contacts 172 and two second contacts 174 are formed in the dielectric layer 170. The first contacts 170 are electrically connected to the metal gate 162 and the source/drain 126 of the transistor 130, and the second contacts 174 are electrically connected to the two metal portions 164 of the resistor 114. It is noteworthy that because the contacts 172, 174 are landing on two different materials (the metal materials of the metal gate 162 and the metal portions 164, and the salicides 128), the contact process is simplified when comparing with the conventional contact process, of which the contacts are landing on three different materials (the metal material of the metal gate, the polysilicon of the resistor, and the salicide formed on the source/drain). Accordingly, the material choice for the contacts is increased and the process window is also improved. Furthermore, because the second contacts 174 contact with the metal portions 164, the surface resistance (Rs) between the second contacts 174 and the resistor 114 is decreased and the stability of the resistor 114 is improved. In the same time, the thermal stability of the resistor 114 is also improved due to the metal portions 164.
According to the manufacturing method for a resistor integrated with a transistor having metal gate, the resistor and the transistor having the metal gate are integrated without increasing process complexity. Furthermore, since the resistor includes the metal portions, the materials contacted to the contacts are simplified and thus the material choice of the contacts is increased and the process window is improved. More important, since the resistor includes the metal portions which possess superior thermal stability, the stability the performance of the resistor are consequently improved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Grant
8477006
