Conventional current-steering techniques have been widely used for high-speed sigma-delta Digital-to-Analog converters (ΣΔ DAC) for deep sub-micron technologies. To meet linearity requirements, unit current cells should be well matched, which requires a large silicon area. Accordingly, transistor matching is becoming more difficult and “area expensive” as processes scale smaller (<22 nm). Alternatively, dynamic element matching or self-current calibration techniques have been conventionally used to compensate for mismatches between unit current DAC cells. These alternative techniques, however, also occupy extra silicon area, while limiting the maximum DAC operation speed. Accordingly, conventional current-steering architectures presently used for DACs are not area-efficient.
Claimed subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. Such subject matter may, however, be understood by reference to the following detailed description when read with the accompanying drawings in which:
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
In the following detailed description, numerous specific details are set forth to provide a thorough understanding of claimed subject matter. It will, however, be understood by those skilled in the art that claimed subject matter may be practiced without these specific details. In other instances, well-known methods, procedures, components and/or circuits have not been described in detail.
In the following description and/or claims, the terms coupled and/or connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical and/or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical and/or electrical contact. “Coupled” may, however, also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate and/or interact with each other. For example, “coupled” may mean that two or more elements do not contact each other but are indirectly joined together via another element or intermediate elements. Finally, the terms “on,” “overlying,” and “over” may be used in the following description and claims. “On,” “overlying,” and “over” may be used to indicate that two or more elements are in direct physical contact with each other. “Over” may, however, also mean that two or more elements are not in direct contact with each other. For example, “over” may mean that one element is above another element but not contact each other and may have another element or elements in between the two elements. Furthermore, the term “and/or” may mean “and”, it may mean “or”, it may mean “exclusive-or”, it may mean “one”, it may mean “some, but not all”, it may mean “neither”, and/or it may mean “both”, although the scope of claimed subject matter is not limited in this respect. In the following description and/or claims, the terms “comprise” and “include,” along with their derivatives, may be used and are intended as synonyms for each other. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments.
The subject matter disclosed herein relates to a digital-to-analog converter (DAC) technology that does not rely on matched current sources for accuracy, but instead utilizes closely matched resistance values for output accuracy. In that regard, the subject matter disclosed herein provides a scaling-compatible DAC architecture. Modern processes (<22 nm) are capable of fabricating for metal gates compact resistors having well-matched resistance values. Accordingly, the same technique to fabricate metal gates can be utilized for fabricating highly linear DACs that comprise a small area and without the flicker noise associated with transistors. Because the effective area of gate resistance is expected to increase with future transistor types, such as tri-gate transistors, the DAC technology disclosed herein would be more area efficient than conventional DAC techniques. Additionally, a one-pole low-pass filter (LPF) can be embedded in the configuration of a DAC according to the subject matter disclosed herein by adding a single capacitor to the output node. Further, a simple slope-control scheme can be included for eliminating even-order harmonics and noise folding caused by duty-cycle distortion for single-ended DAC implementation.
VDD×(R×MSB×21+2R×LSB×20)/3R, (1)
yielding an output of 0, ⅓VDD, ⅔VDD and VDD, in which VDD is the supply voltage of the inverters 102 and 103.
The topology of DAC 100 provides constant output impedance Zout, which in the exemplary configuration depicted in
Flip-flops 202 and 203 ensure that bits B1 and B0 are synchronized with a DAC clock clk. There could be, however, a mismatch between the clock-to-Q-delay, when the FF output transitions from low to high, and vice versa. This mismatch creates a duty-cycle distortion resulting in even-order harmonics plus a high-frequency noise folding. A fully differential implementation of resistor-based ΣΔ DAC 200 can eliminate the duty-cycle distortion problem, but when a single-ended DAC configuration is necessary, a calibration scheme is required. For example, the code-dependent clock-to-Q-delay mismatch can be calibrated by separately controlling rising and falling time of the outputs of FFs 202 and 203. Slope-control logic 204 and 205 can be implemented by a digitally controlled current-starved inverter, as shown in
The ΣΔ DAC according to the subject matter disclosed herein can be extended to multi-bit (i.e., more than 2-bit) design by parallelization.
Binary multi-bit ΣΔ DAC 500, depicted in
The thermometric multi ΣΔ DAC 550, depicted in
Filtering performance of a ΣΔ DAC according to the subject matter disclosed herein can be improved by a semi-digital operation, such as, by parallelizing a plurality of L unit DACs using L-1-stage registers, as depicted by ΣΔ DAC 600 in
Although the claimed subject matter has been described with a certain degree of particularity, it should be recognized that elements thereof may be altered by persons skilled in the art without departing from the spirit and/or scope of claimed subject matter. The claimed subject matter will be understood by the forgoing description, and it will be apparent that various changes may be made in the form, construction and/or arrangement of the components thereof without departing from the scope and/or spirit of the claimed subject matter or without sacrificing all of its material advantages, the form herein before described being merely an explanatory embodiment thereof, and/or further without providing substantial change thereto. It is the intention of the claims to encompass and/or include such changes.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/US2011/054297 | 9/30/2011 | WO | 00 | 6/17/2013 |
Publishing Document | Publishing Date | Country | Kind |
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WO2013/048450 | 4/4/2013 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
3906489 | Schlichte | Sep 1975 | A |
4603319 | Hinn | Jul 1986 | A |
5021785 | Kohdaka et al. | Jun 1991 | A |
5231395 | Irwin et al. | Jul 1993 | A |
6204789 | Nagata | Mar 2001 | B1 |
20020080053 | Brooks et al. | Jun 2002 | A1 |
20050073453 | Cheng et al. | Apr 2005 | A1 |
Number | Date | Country |
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2013048450 | Apr 2013 | WO |
Entry |
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International Search Report and Written opinion for PCT Patent Application No. PCT/US2011/054297, mailed on May 4, 2012, 8 Pages. |
International Preliminary Report on Patentability and Written Opinion received for PCT Patent Application No. PCT/ US2011/054297, mailed on Apr. 10, 2014, 5 pages. |
Number | Date | Country | |
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20130271305 A1 | Oct 2013 | US |