The present invention relates to memory devices. In particular, the present invention relates to a memory device with a gate-injected charge storage layer.
Memory devices with a gate-injected charge-storage layer have been disclosed, for example, in the article entitled “A Novel Gate Injection Program/Erase P-channel NAND type Flash Memory with High (10M cycle) Endurance” (“Lue”), by Hang-Ting Lue et al., and published in the 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 140-141. Lue discloses a p-channel memory cell. Lue is constrained to a p-channel memory cell to take advantage of a self-boosting technique in a program-inhibit method that requires a reversed polarity in the drain-body junction to avoid program disturb. Lue's device is complex with respect to processing, design and programming and erasing operations. Being constrained to use a p-channel memory cell is also very limiting. For example, a p-channel memory cell has a lower cell current, due to the low mobility inherent in hole conduction, as compared to the high mobility inherent in the electron conduction in an n-channel cell. The channel, drain and source electrodes of Lue's memory cell are also formed in a silicon substrate. Thus, Lue's memory cell cannot be used as a building block of a 3-dimensional memory array.
For programming and erase operations, Lue's memory cell requires both positive and negative voltages. Specifically, Lue's memory cell requires a negative voltage (e.g., −19 volts) for programming operations and a positive voltage (e.g., 19 volts) for erase operations. Requiring both positive and negative polarities with relatively high magnitudes (e.g., 19 volts) increases design and process complexities (e.g., requiring a triple-well process and array decoding circuits). These requirements impose a significantly higher memory cost relative to conventional non-volatile channel-injected charge memory cells.
According to one embodiment of the present invention, a thin-film memory cell includes (a) first and second deposited semiconductor layers of a first conductivity type; (b) a third deposited semiconductor layer of a second conductivity type provided between the first and second deposited semiconductor layers; (c) a first dielectric layer adjacent the third deposited semiconductor layer; (d) a charge-trapping layer adjacent the first dielectric layer, the first dielectric layer separating the charge-trapping layer from the third deposited semiconductor layer; (e) a second dielectric layer adjacent the charge-trapping layer and spaced apart from the first dielectric layer by the charge-trapping layer; and (f) a conductive layer adjacent the second dielectric layer and spaced apart from the charge-trapping layer by the second dielectric layer, wherein the first and second dielectric layers have a different in layer thickness such that, when a sufficiently large potential difference is imposed between the conductive layer and the third deposited semiconductor layer, electric charge is exchanged between the conductive layer and the charge-trapping layer by tunneling through the second dielectric layer.
In various embodiments of the present invention, the conductive layer of the thin-film memory cell may be formed out of P+-type or N+-type polysilicon. In some embodiments, the first and second deposited semiconductor layers may each be P+-type polysilicon, while the third deposited semiconductor layer may be N−-type polysilicon. In other embodiments, the first and second deposited semiconductor layers may each be N+-type polysilicon, while the third deposited semiconductor layer may be P−-type polysilicon. The charge-trapping layer may include silicon nitride, while the first and second dielectric layers each include silicon oxide.
In a thin-film memory cell of the present invention, the first, second and third deposited semiconductor layers serve, respectively, as a source electrode, a drain electrode and a channel region for the thin-film memory cell, the conductive layer serves as a gate electrode for the thin-film memory cell, and the charge-trapping layer serves as storage layer for the thin-film memory cell.
According to one embodiment of the present invention, the thin-film memory cell may be used as a building block for a three-dimensional memory array. In one exemplary configuration, a number of thin-film memory cells are formed in a deposited semiconductor structure (“an active strip”) extending along a direction parallel to a planar surface of a semiconductor substrate. A number of such active strips may be stacked one on top of another—isolated from each other by dielectric layers—along a direction perpendicular to the semiconductor substrate. In one such embodiment, a number of conductive columns are provided extending along the direction perpendicular to the semiconductor substrate, each being placed adjacent the active strips, such that each conductive column serves as a common gate electrode to a memory cell in each of the adjacent active strips.
According to one embodiment of the present invention, a thin-film memory cell may be programmed, erased, read, program-inhibited and erase-inhibited by applying predetermined voltages of the same polarity relative to a ground reference voltage to the source electrode, the drain electrode, and the gate electrode.
The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.
The present invention provides a non-volatile “reverse memory cell” for a 3-dimensional memory array. In this detailed description, the term “reverse memory cell” refers to a memory cell that includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. A reverse memory cell of the present invention may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell of the present invention using only one polarity of voltages: i.e., only positive voltages for an N-channel reverse memory cell and only negative voltages for P-channel reverse memory cell, thereby simplifying both the design and the power management operations.
The Non-provisional Patent Application, incorporated by reference above, discloses structures, including memory cells, for forming 3-dimensional memory arrays and methods for fabricating such structures. For example, one of such structures is illustrated in FIGS. 5h-1 to 5h-3 of the Non-provisional Patent Application.
As shown in
Programming and erase operations in a memory array are typically performed in parallel (i.e., at the same time) for many memory cells. Because there are inevitably small variations in the values of geometrical and electrical parameters among the memory cells (e.g., due to local variations in the process), distributions in the natural cell threshold voltage values and threshold voltage values in the memory cells result after repeated programming and erase operations. The distributions may be narrowed (e.g., through programming and erasing algorithms) generally to any extent desired through suitable control, at the expense of programming, erase time or both.
As shown in
Another approach for programming a reverse memory cell is to apply a succession of shorter duration stepped voltage pulses to the common source and the common drain electrodes, while the gate electrode is held at 0 volts. The stepped voltage pulses may start at around 10 volts and increases in multiple voltage increments to as high as 20 volts. After each programming pulse, a program-verify operation is performed to determine the cell threshold voltage. If the target cell threshold voltage has not been reached, a next programming pulse, incremented from the last programming pulse typically by a few hundred millivolts, is applied across the common source and the common drain electrodes. This programming and program-verify operation sequence is continued until the reverse memory cell reaches the target cell threshold voltage.
As discussed above, programming of many memory cells may be performed in parallel. Thus, a memory cell which is not intended to be programmed, or which has reached its desired or target cell threshold voltage, must be prevented from programming or further programming by a program-inhibit operation. To inhibit programming of the reverse memory cell, the gate electrode is biased to a predetermined voltage, such that the voltage difference between the gate electrode and either of the common source and the common drain electrodes is not enough to unintentionally effectuate programming. This predetermined voltage may be, for example, half the programming voltage (e.g., 5-10 volts).
During an erase operation, as shown in
To prevent erasing a reverse memory cell or to prevent a satisfactorily erased reverse memory cell from being subject to a further erase operation, inhibit voltages need to be applied. Erase inhibition may be achieved by biasing the common source and the common drain electrodes to a voltage such that, when the erase pulse is applied to the gate electrode, the voltage difference between the gate electrode and either one of the common source and the common drain electrodes is less than the voltage sufficient to achieve erasing (e.g., half the erase voltage, or 5-10 volts). In this configuration all reverse memory cells in an active strip sharing the common source electrode or common drain electrode would be prevented from successfully erased.
Another approach for erasing is to apply a succession of shorter duration, stepped voltage pulses to the gate electrode, while keeping the common source and the common drain electrodes at 0 volts. The stepped voltage pulses may start at around 10 volts and may go as high as 20 volts. After each erase pulse, an erase-verify operation is performed to determine the cell threshold voltage. If the target cell threshold voltage has not been reached, a next erase pulse, incremented from the last erase pulse typically by a few hundred millivolts, is applied to the gate electrode. This erase and erase-verify operation sequence is continued until the reverse memory cell reaches the target cell threshold voltage.
Yet another approach for erasing is to apply a single long erase pulse on the gate electrode (i.e., greater than 20 microseconds) on each reverse memory cell to be erased. Thereafter, a soft programming operation may be performed on each reverse memory cell with a threshold voltage that is lower that the erase target cell threshold voltage. In this manner, each reverse memory cell may be erased to achieve the desired erase cell threshold value.
The memory cell of
As the injection and extraction of electrons and holes during the program and erase operations in the reverse memory cell of
The thicknesses of tunnel oxide 206 and nitride trapping layer 107 of a reverse memory cell may be optimized for certain applications. For example, the thicknesses of these layers may be set to achieve both read disturb and to carry out reliable low-voltage programming operations (e.g., voltages below 10 volts). As another example, tunnel oxide layer 206 may be made sufficiently thin to allow direct tunneling, rather than Fowler-Nordheim tunneling, at the desired programming or erase voltage (e.g., less than 10 nm). In certain applications, e.g., quasi-volatile memory (QVM) applications, greater tolerance may be traded off for a lesser retention time (e.g., minutes, rather than days or years, to allow endurance of tens of thousands of cycles or more). In those applications, nitride trapping layer 107 may be made thinner to optimize for the desired endurance and retention time.
The memory cell of the present invention may be implemented, for example, as a memory cell in the structure shown in
Each active strip is shown in
N+ sublayer 221 is either hard-wire connected to a ground voltage (not shown), or is not directly connected to an outside terminal and left floating, or pre-charged to a voltage (e.g., a ground voltage) during a read operation. Pre-charging may be achieved by activating local pre-charge word lines 208-CHG. P− sublayer 222 of each active layer (providing the channel regions of Ms) is optionally selectively connected through pillars 290 (described below) to supply voltage Vbb in substrate 201, Metallic sublayer 224 is an optional low resistivity conductor, provided to reduce the resistivity of active layers 202-4 to 202-7. To simplify, interlayer isolation layers 203-0 and 203-1 of
Global word lines 208 a-a on top of the memory array are formed by depositing, patterning and etching a metal layer following the formation of contacts or vias. Such a metal layer may be provided by, first, forming a thin tungsten nitride (TiN) layer, followed by forming a low resistance metal layer (e.g., metallic tungsten). The metal layer is then photo-lithographically patterned and etched to form the top global word lines. (Alternatively, these global word lines may be provided by a copper damascene process.) In one implementation, these global word lines are horizontal, running along the X-direction and electrically connecting the contacts formed in the isolation oxide (i.e., thereby contacting local word lines 208W-a or 208W-CHG) and with the contacts to semiconductor substrate 201 (not shown). Other mask and etch process flows known to those of ordinary skill in the art are possible to form even and odd addressed local word lines and connect them appropriately to their global word lines, either from the top of the memory array through the top global word lines or from the bottom of the memory array through the bottom global word lines (and, in some embodiments, from both top and bottom global word lines).
The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the accompanying claims.
The present application relates to and claims priority of U.S. provisional patent application (“Provisional Application”), Ser. No. 62/588,097, entitled “REVERSE MEMORY CELL,” filed on Nov. 17, 2017. The present application relates also to U.S. patent application (“Non-provisional Patent Application”), Ser. No. 15/248,420, entitled “Capacitive-coupled Non-Volatile Thin-film Transistor Strings in Three-Dimensional Arrays,” filed on Aug. 29, 2016. The disclosures of the Provisional Application and the Non-provisional Patent Application are hereby incorporated by reference in their entireties.
Number | Name | Date | Kind |
---|---|---|---|
3851317 | Kenyon | Nov 1974 | A |
4760556 | Deguchi et al. | Jul 1988 | A |
5583808 | Brahmbhatt | Dec 1996 | A |
5646886 | Brahmbhatt | Jul 1997 | A |
5768192 | Eitan | Jun 1998 | A |
6040605 | Sano | Mar 2000 | A |
6130838 | Kim et al. | Oct 2000 | A |
6434053 | Fujiwara | Aug 2002 | B1 |
6580124 | Cleeves et al. | Jun 2003 | B1 |
6744094 | Forbes | Jun 2004 | B2 |
6946703 | Ryu et al. | Sep 2005 | B2 |
7005350 | Walker et al. | Feb 2006 | B2 |
7233522 | Chen et al. | Jun 2007 | B2 |
7612411 | Walker et al. | Nov 2009 | B2 |
8026521 | Or-Bach et al. | Sep 2011 | B1 |
8630114 | Lue | Jan 2014 | B2 |
8878278 | Alsmeier et al. | Nov 2014 | B2 |
9842651 | Harari | Dec 2017 | B2 |
9892800 | Harari | Feb 2018 | B2 |
9911497 | Harari | Mar 2018 | B1 |
10074667 | Higashi | Sep 2018 | B1 |
10096364 | Harari | Oct 2018 | B2 |
10121553 | Harari | Nov 2018 | B2 |
10249370 | Harari | Apr 2019 | B2 |
10254968 | Gazit et al. | Apr 2019 | B1 |
10381378 | Harari | Aug 2019 | B1 |
10395737 | Harari | Aug 2019 | B2 |
10431596 | Herner et al. | Oct 2019 | B2 |
10475812 | Harari | Nov 2019 | B2 |
10622377 | Harari et al. | Apr 2020 | B2 |
20010030340 | Fujiwara | Oct 2001 | A1 |
20010053092 | Kosaka | Dec 2001 | A1 |
20020051378 | Ohsawa | May 2002 | A1 |
20020193484 | Albee | Dec 2002 | A1 |
20040246807 | Lee | Dec 2004 | A1 |
20050128815 | Ishikawa | Jun 2005 | A1 |
20060155921 | Gorobets et al. | Jul 2006 | A1 |
20070230234 | Ohsawa | Oct 2007 | A1 |
20080239812 | Abiko | Oct 2008 | A1 |
20090157946 | Arya | Jun 2009 | A1 |
20090237996 | Kirsch et al. | Sep 2009 | A1 |
20090279360 | Lee | Nov 2009 | A1 |
20090316487 | Lee et al. | Dec 2009 | A1 |
20100124116 | Maeda | May 2010 | A1 |
20110208905 | Shaeffer et al. | Aug 2011 | A1 |
20110298013 | Hwang | Dec 2011 | A1 |
20120182801 | Lue | Jul 2012 | A1 |
20120243314 | Maeda | Sep 2012 | A1 |
20130007740 | Kato et al. | Mar 2013 | A1 |
20130256780 | Kai | Oct 2013 | A1 |
20140117366 | Saitoh | May 2014 | A1 |
20140151774 | Rhie | Jun 2014 | A1 |
20140328128 | Louie et al. | Nov 2014 | A1 |
20140340952 | Ramaswamy et al. | Nov 2014 | A1 |
20150131381 | Rhie | May 2015 | A1 |
20150194440 | Noh et al. | Jul 2015 | A1 |
20160086970 | Peng | Mar 2016 | A1 |
20160314042 | Plants | Oct 2016 | A1 |
20170092370 | Harari | Mar 2017 | A1 |
20170148810 | Kai et al. | May 2017 | A1 |
20170358594 | Lu et al. | Dec 2017 | A1 |
20180108416 | Harari | Apr 2018 | A1 |
20180269229 | Or-Bach et al. | Sep 2018 | A1 |
20180366471 | Harari et al. | Dec 2018 | A1 |
20180366489 | Harari et al. | Dec 2018 | A1 |
20190006009 | Harari | Jan 2019 | A1 |
20190180821 | Harari | Jun 2019 | A1 |
20190206890 | Harari et al. | Jul 2019 | A1 |
20190244971 | Harari | Aug 2019 | A1 |
20190325964 | Harari | Oct 2019 | A1 |
20190319044 | Harari | Nov 2019 | A1 |
20190355747 | Herner et al. | Nov 2019 | A1 |
20190370117 | Fruchtman et al. | Dec 2019 | A1 |
20200051990 | Harari et al. | Feb 2020 | A1 |
20200098779 | Cernea et al. | Mar 2020 | A1 |
20200176468 | Herner et al. | Jun 2020 | A1 |
Number | Date | Country |
---|---|---|
2018236937 | Dec 2018 | WO |
Entry |
---|
PCT Search Report and Written Opinion, PCT/US2018/038373, dated Sep. 10, 2018. |
“Partial European Search Report EP 16869049.3”, dated Jul. 11, 2019, pp. 1-12. |
“Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage” by W. Kim et al., published in the 2009 Symposium on VLSI Tech. Dig. of Technical Papers, pp. 188-189. |
“A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” by H.T. Lue et al., published in the 2010 Symposium on VLSI: Tech. Dig. of Technical Papers, pp. 131-132. |
“High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application”, by H.C. Wann and C.Hu, published in IEEE Electron Device letters, vol. 16, No. 11, Nov. 1995, pp. 491-493. |
International Search Report and Written Opinion, PCT/US2016/060457, dated Apr. 13, 2017. |
“EP Extended Search Report EP168690149.3”, dated Oct. 18, 2019. |
Number | Date | Country | |
---|---|---|---|
20190157296 A1 | May 2019 | US |
Number | Date | Country | |
---|---|---|---|
62588097 | Nov 2017 | US |