1. Field of the Invention
The present invention relates to processor registers and more particularly, to a method of expanding the capacity of RISC processor registers.
2. Description of the Related Art
In RISC processor registers, the register fields of the normal instruction format employs direct encoding, therefore the encoding space for the register fields of the normal instruction format directly affects the amount of the architectural registers. Increasing the encoding space for the register fields can improves the amount of the architectural registers, however the whole code size will be relatively increased. Further, increasing the encoding space for the register fields means an increase of the length of instructions. These instructions will become more complicated in the pipeline decode stage, increasing power consumption of the processor. To embedded processors that emphasize the factors of power consumption and storage space, the aforesaid result is contrary to what is expected.
The major processors in the market, such as MIPS, ARM, Alpha, THUMB, X86, UltraSPARC and Power, commonly have 8˜32 architectural registers, i.e., the encoding space of the register fields is about 3˜5 bits. This arrangement limits the amount of the usable architectural registers, causing a bottleneck in program execution efficiency improvement.
Current researches and techniques to improve the usable amount of architectural registers are focused on adding hardware. However, adding hardware brings certain side effects, such as increasing the hardware cost, complicating the hardware design, limiting the applicability to specific platforms and lowering the flexibility in use.
In conclusion, the known techniques have the drawbacks as follows:
The present invention has been accomplished under the circumstances in view. It is the main object of the present invention to provide a method of expanding the capacity of RISC processor registers, which breaks through instruction format limits, effectively improves the use of architectural registers on different platforms, and greatly enhances program execution efficiency.
To achieve this and other objects of the present invention, a RISC processor register expansion method comprises the steps of: a) designing an instruction format having multiple register fields to have the total bits consumed by the register fields to be designed into two bits combinations respectively corresponding to two register banks, wherein the first bits combination has 8 bits of which the value of the 1st˜7th bits is adapted to designate the location (0-127) of the first register field in one of the two register banks and the value of the 8th bit is adapted to designate which one of the two register banks the first register field is to be allocated, and the second bits combination has at least 2 bits; b) defining an operation instruction without exchangeability to be an inverse operation instruction wherein the inverse operation instruction is to swap the operand variables in the two register banks in the same position prior to computing, eliminating the problem of a different operation result due to the order of the register banks on which the operand variables are allocated; and c) designing a register allocation algorithm to pick up one respective operand variable from each of the two register banks and to join the two operand variables into a node. The register allocation algorithm comprises the steps of: c1) checking the relationship between the two operands in the current node and the operands of the other nodes to be the same or partially different, and then proceeding to step c2) when partially different, or step c3) when the same, and then searching the storable position in the two register banks when neither the aforesaid relationship condition exists; c2) searching for the other nodes that have the operands therein partially same as the two operands of the current node, and then checking the operands of the searched nodes that are different from the operands of the current node to be empty or to have another different relationship and then using the searched node and transferring the operands from the current node to the searched node and then deleting the current node; c3) searching for the other nodes that have the operands therein to be same as the two operands of the current node and then deleting the current node when a node that has the operands therein to be same as the two operands of the current node is found; and c4) determining whether or not to change the operation instruction into an inverse operation instruction subject to the nature of the operation instruction.
Thus, this RISC processor register expansion method breaks through instruction format limits, raises the number of bits and effectively enhances the use of architectural registers. Further, this RISC processor register expansion method is applicable to different platforms and greatly enhances the program execution efficiency without increasing the instruction code size.
Other and further advantages, benefits and features of the present invention will be fully understood by reference to the following specification in conjunction with the accompanying drawings.
Referring to
a) As shown in
b) Define operation instructions without exchangeability to be inverse operation instructions. To an operation instruction having an exchange characteristic (for example, the add instruction), the order of the register bank (15) or (16) on which the operand variable is located does not affect the final execution result (see
c) As shown in
Further, to every D-node, it is necessary to find the next node that uses its operand variables and then to draw a real line and an arrow to denote this dependent relationship; to every G-node, use an imaginary line to indicate the relationship and then calculate the weighted value of the same relationship and mark the weighted value on the first G-node, and then find whether or not the first G-node and the last G-node are partially dependent to the other D-nodes, and then draw a real line and an arrow to denote the partially dependent relationship, if any. The relationship of the aforesaid real line, imaginary line and arrow are shown in
The aforesaid register allocation algorithm includes the steps of:
c1) Check the relationship between the two operand variables of the current node and the operand variables of the other nodes to be of the same relationship (G-node) or partially different (D-node), and then proceed to step c2) if partially different, or step c3) if the same. If without any of the aforesaid relationships (for example, completely different), find a storable location from the two register banks (15) and (16).
c2) Based on the two operands in the current node, search the other D-nodes of which the operand variables are partially same as the two operands of the current node, and then check whether or not the operand variables of the searched D-node that are different from the current node are empty or have any other relationship, if the searched D-node is empty or have any other relationship, use the searched node and transfer the operand variables from the current node to the searched node when positive, and then delete the current node after transfer of the operand variables.
c3) Search for the other G-nodes that have the operands therein to be same as the two operands of the current node, and then deleting the current node when a node that has the operands therein to be same as the two operands of the current node is found.
c4) Determine, subject to the nature of the operation instruction, whether or not to change the instruction into an inverse operation instruction.
Directly allocate the operand variables to the assigned register banks (15) and (16) when executing step i1 after establishment of the NDG.
When executing step i2, due to the fact that A in D-node has a partially dependent relationship, check the last node that used A to see if the location for the right side operand variable is empty or it does not have a partially dependent relationship. When it meets the aforesaid condition, transfer X to the location of this node for the right side operand variable when it meets the aforesaid condition, and then delete the dependent real line and arrow and the original node from the NDG. Further, it is necessary to check whether or not to change the operation into an inverse operation instruction.
When executing step i3, due to all the nodes belong to G-nodes, it is not necessary to make any transfer. During this step, it simply needs to check whether or not the operation is exchangeable and the locations of the operand variables of the G-nodes in the register banks (15) and (16) are same. Based on the aforesaid conditions, determine whether or not to change the instruction into an inverse operation instruction. Because the operation of this step i3 is an add operation having exchangeability, it is not necessary to change the operation into an inverse operation instruction. It simply needs to deduct 1 from the weighted value of the G-node and to delete the imaginary line relationship and the node produced during step i3. At this time, the weighted value of the G-node which is deducted from that of the last one has become 1, and therefore the G-node is converted into a D-node to facilitate further operation.
When executing step i4, search the last node which used the operand variable C subject to the partially dependent characteristic of the D-node. At this time, check whether or not the left side operand variable location of this node is empty or it does not have the partially dependent relationship. When it meets the aforesaid condition, transfer the operand variable E to the original location for the operand variable B and then delete the real line and arrow head and the original node from the NDG. Further, it also needs to check whether or not to convert this operation into an inverse operation instruction.
When executing step i5, search the last node which used the operand variable A subject to the partially dependent characteristic of the D-node. At this time, check whether or not the right side operand variable location of this node is empty or if the right side operand variable location of this node does not have the partially dependent relationship. When it meets the aforesaid condition, transfer the operand variable D to the original location for the operand variable X and then delete the real line and arrow head and the original node from the NDG. Further, it also needs to check whether or not to convert this operation into an inverse operation instruction. We discovered that the operation of step i5 is a deduction operation without exchangeability and we also discovered the locations of the operand variables of the node in the register banks (15) and (16) and the related instruction. Therefore, the operation instruction of this step i5 must be converted into an inverse operation instruction Rsub.
Subject to the design of the aforesaid instruction format (10) and the definition of the inverse operation instruction and the register allocation algorithm, the allocation of the original registers is re-designed without changing the real register structure, enabling the number of registers to be increased from 3˜5 bits (i.e., 8˜32 registers) to 7 bits (128 registers). Thus, this method effectively achieves the desired register expansion effect. Through the explanation of
As shown in
The relationship between the register field Rs and the register field Rt is explained hereinafter with reference to
The other steps of this second embodiment are same as that of the aforesaid first embodiment, and therefore no further detailed description in this regard is necessary.
When executing step i1 and step i2 after establishment of the NDG, allocate the position of every node in the register bank (25) or (26) subject to the NDG.
When executing step i3, search the last node that used the operand variable A subject to the partially dependent characteristic of the D-node. At this time, the partially dependent relationship of the right side operand variable B of this node is discovered, i.e., there is another instruction going to use this operand variable B, and therefore it is not to be substituted. So, the second best is to check the position in the register bank (25) or (26) in front of the operand variable B and the position in the register bank (25) or (26) next to the operand variable B to be empty or to have a partially dependent relationship. If the position in front of or next to the operand variable B is empty or does not have a partially dependent relationship, use one of the positions for the transfer of the operand variable C during step i3. In this example, we found that the position 0 in the second register bank (25) or (26) and the position 2 in the register bank (25) or (26) are usable, and therefore the position 0 in the second register bank (25) or (26) is used for the transfer of the operand variable C. Thereafter, modify the relationship of the nodes in the NDG relative to the operand variable C.
From the description of the aforesaid two embodiments, the invention achieves the effects of: breaking through instruction format limits, raising the number of bits and effectively enhancing the use of architectural registers. Further, the invention is applicable to different platforms and greatly enhances the program execution efficiency without increasing the instruction code size.