SAMPLING DEVICE, DISPLAY DEVICE USING SAMPLING DEVICE, AND CAMERA

Abstract

A correction sampling signal generation circuit is disposed subsequent to a plural-stage sampling signal generation circuit of sequentially generating sampling signals in response to an input timing signal, an extended sampling circuit is disposed subsequent to a plural-stage sampling circuit of sampling a video signal at timing of the sampling signal, and a data signal is sampled at timing of the sampling signal generated by the extended sampling circuit. In a timing adjustment period, the data signal for adjustment is generated, the phases of the data signal and the timing signal are relatively shifted, the outputs of the sampling circuits are supplied to a common output line through respective switches, and the phase of the optimum timing signal or the video signal is determined based on the output from the common output line.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for describing a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart for describing the operation in FIG. 1.

FIG. 3 is a diagram for describing sampling phase detection in the first exemplary embodiment.

FIG. 4 is a block diagram for describing a second exemplary embodiment of the present invention.

FIG. 5 is a timing chart for describing the operation in FIG. 4.

FIG. 6 is a diagram for describing sampling phase detection in the second exemplary embodiment.

FIG. 7 is a block diagram for describing a third exemplary embodiment of the present invention.

FIG. 8 is a diagram for describing sampling phase detection in the third exemplary embodiment.

FIG. 9 is a block diagram for describing a fourth exemplary embodiment of the present invention.

FIG. 10 is a block diagram chart for describing the operation to be executed in a correction period according to the fourth exemplary embodiment.

FIG. 11 is a timing chart for describing the operation to be executed in a period A illustrated in FIG. 10.

FIG. 12 is a timing chart for describing the operation to be executed in a period B illustrated in FIG. 10.

FIG. 13 is a diagram for describing sampling phase detection in the period A according to the fourth exemplary embodiment.

FIG. 14 is a diagram for describing sampling phase detection in the period B according to the fourth exemplary embodiment.

FIG. 15 is a diagram for describing the sampling phase detection in the fourth exemplary embodiment.

FIG. 16 is a block diagram illustrating an example of a digital still camera.

Claims

1. A sampling device comprising: (a) a timing signal generation circuit adapted to generate a timing signal delayed with respect to a reference clock signal;(b) a control circuit adapted to control a delay time of the timing signal;(c) a data generation circuit adapted to generate a serial data signal;(d) an N-stage shift register, to which the timing signal is input, adapted to sequentially generate sampling pulses in sync with the timing signal;(e) a sampling circuit, connected to any one of the stages of the shift register and the data generation circuit, adapted to sample the serial data signal during a period that the sampling pulse of the relevant stage is generated, and to output a current according to a sampling result; and(f) a common output line commonly connected to respective current outputs of the sampling circuit through a switch,wherein the sampling circuit includes M sampling circuits respectively connected to continuous first to M-th (<N) stages of the N-stage shift register, and a sampling circuit connected to a last stage of the shift register,A. following operations (1) to (3) are executed during a period that the switch is closed,(1) the data generation circuit generates N serial data signals of which the last is data giving a maximum current and others are data giving a minimum current,(2) the timing signal generation circuit generates the timing signal delayed with respect to the reference clock signal, and(3) the control circuit measures an output current of the common output line as sweeping the delay time of the timing signal, and decides and stores the delay time that the measured current becomes maximum within a range of the sweeping, andB. following operations (4) to (6) are executed during a period that the switch is released,(4) the control circuit fixes the delay time of the timing signal to the stored delay time,(5) the data generation circuit generates the serial data signal based on an externally input signal, and(6) the timing signal generation circuit generates the timing signal on the fixed delay time to the serial data signal based on the externally input signal.

2. A sampling device according to claim 1, wherein M<N−1, anda sampling circuit of which the output is not connected to the common output line through the switch is provided between the M sampling circuits and the sampling circuit connected to the last stage of the shift register.

3. A sampling device according to claim 1, wherein M<N−1, anda sampling circuit is not provided between the M sampling circuits and the sampling circuit connected to the last stage of the shift register.

4. A sampling device according to claim 1, wherein M<N−1, anda sampling circuit, which is connected to the stage one-previous to the last stage of the shift register and of which the output is connected to the common output line through the switch, is provided between the M sampling circuits and the sampling circuit connected to the last stage of the shift register.

5. A sampling device according to claim 1, wherein, in the operation (3), the control circuit sweeps the delay time in order from shorter to longer.

6. A display device which includes a sampling device comprising: (a) a timing signal generation circuit adapted to generate a timing signal delayed with respect to a reference clock signal;(b) a control circuit adapted to control a delay time of the timing signal;(c) a data generation circuit adapted to generate a serial data signal;(d) an N-stage shift register, to which the timing signal is input, adapted to sequentially generate sampling pulses in sync with the timing signal;(e) a sampling circuit, connected to any one of the stages of the shift register and the data generation circuit, adapted to sample the serial data signal during a period that the sampling pulse of the relevant stage is generated, and to output a current according to a sampling result; and(f) a common output line commonly connected to respective current outputs of the sampling circuit through a switch,wherein the sampling circuit includes M sampling circuits respectively connected to continuous first to M-th (<N) stages of the N-stage shift register, and a sampling circuit connected to a last stage of the shift register,A. following operations (1) to (3) are executed during a period that the switch is closed,(1) the data generation circuit generates N serial data signals of which the last is data giving a maximum current and others are data giving a minimum current,(2) the timing signal generation circuit generates the timing signal delayed with respect to the reference clock signal, and(3) the control circuit measures an output current of the common output line as sweeping the delay time of the timing signal, and decides and stores the delay time that the measured current becomes maximum within a range of the sweeping, andB. following operations (4) to (6) are executed during a period that the switch is released,(4) the control circuit fixes the delay time of the timing signal to the stored delay time,(5) the data generation circuit generates the serial data signal based on an externally input signal, and(6) the timing signal generation circuit generates the timing signal on the fixed delay time to the serial data signal based on the externally input signal,wherein the display device comprises a display panel which includes: plural scanning electrodes extending in a row direction; M-column column electrodes intersecting the scanning electrodes; andplural pixels respectively arranged on an intersection portion of the scanning electrodes and the column electrodes, andwherein, while the switch is being opened, the output terminals of the M sampling circuits are respectively connected to the M-column column electrodes.

7. A display device according to claim 6, wherein a period that the switch is closed is set within a turn-off period of the display device.

8. A camera comprising: a display device which includes a sampling device comprising: (a) a timing signal generation circuit adapted to generate a timing signal delayed with respect to a reference clock signal;(b) a control circuit adapted to control a delay time of the timing signal;(c) a data generation circuit adapted to generate a serial data signal;(d) an N-stage shift register, to which the timing signal is input, adapted to sequentially generate sampling pulses in sync with the timing signal;(e) a sampling circuit, connected to any one of the stages of the shift register and the data generation circuit, adapted to sample the serial data signal during a period that the sampling pulse of the relevant stage is generated, and to output a current according to a sampling result; and(f) a common output line commonly connected to respective current outputs of the sampling circuit through a switch,wherein the sampling circuit includes M sampling circuits respectively connected to continuous first to M-th (<N) stages of the N-stage shift register, and a sampling circuit connected to a last stage of the shift register,A. following operations (1) to (3) are executed during a period that the switch is closed,(1) the data generation circuit generates N serial data signals of which the last is data giving a maximum current and others are data giving a minimum current,(2) the timing signal generation circuit generates the timing signal delayed with respect to the reference clock signal, and(3) the control circuit measures an output current of the common output line as sweeping the delay time of the timing signal, and decides and stores the delay time that the measured current becomes maximum within a range of the sweeping, andB. following operations (4) to (6) are executed during a period that the switch is released,(4) the control circuit fixes the delay time of the timing signal to the stored delay time,(5) the data generation circuit generates the serial data signal based on an externally input signal, and(6) the timing signal generation circuit generates the timing signal on the fixed delay time to the serial data signal based on the externally input signal,wherein the display device comprises a display panel which includes: plural scanning electrodes extending in a row direction;M-column column electrodes intersecting the scanning electrodes; andplural pixels respectively arranged on an intersection portion of the scanning electrodes and the column electrodes, andwherein, while the switch is being opened, the output terminals of the M sampling circuits are respectively connected to the M-column column electrodes;an imaging unit adapted to capture a subject; andan image signal processing unit adapted to process an image signal captured by the imaging unit,wherein the image signal processed by the image signal processing unit is displayed on the display device.

9. A sampling device comprising: (a) a timing signal generation circuit adapted to generate a timing signal delayed with respect to a reference clock signal;(b) a control circuit adapted to control a delay time of the timing signal;(c) a data generation circuit adapted to generate a serial data signal;(d) an N-stage shift register, to which the timing signal is input, adapted to sequentially generate sampling pulses in sync with the timing signal;(e) a sampling circuit, connected to any one of the stages of the shift register and the data generation circuit, adapted to sample the serial data signal during a period that the sampling pulse of the relevant stage is generated, and to output a current according to a sampling result; and(f) a common output line commonly connected to respective current outputs of the sampling circuit through a switch, wherein the sampling circuit includes M sampling circuits respectively connected to continuous M (<N) stages of the shift register including a last stage of the N-stage shift register, and a sampling circuit connected to a first stage of the shift register,A. following operations (1) to (3) are executed during a period that the switch is closed,(1) the data generation circuit generates N serial data signals of which the head is data giving a maximum current and others are data giving a minimum current,(2) the timing signal generation circuit generates the timing signal delayed with respect to the reference clock signal, and(3) the control circuit measures an output current of the common output line as sweeping the delay time of the timing signal, and decides and stores the delay time that the measured current becomes maximum within a range of the sweeping, andB. following operations (4) to (6) are executed during a period that the switch is released,(4) the control circuit fixes the delay time of the timing signal to the stored delay time,(5) the data generation circuit generates the serial data signal based on an externally input signal, and(6) the timing signal generation circuit generates the timing signal on the fixed delay time.