Sampling rate mismatch solution

Abstract

Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer timing modification, a buffer clock signal is interrupted as needed to slow the rate of data through the buffer. In sample addition, pseudo samples are inserted into a data stream to compensate for timing differences.

Description

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

In the drawings:

FIG. 1 is a block diagram illustrating part of a typical communication system;

FIG. 2 is a timing diagram that illustrates differences in transmitter and receiver sample rates;

FIG. 3 is a block diagram of a receiver including a switch;

FIG. 4 is a flow chart of a method of switch operation;

FIG. 5 is a timing diagram of an exemplary receiver clock signal and modified receiver clock signals;

FIG. 6 is a block diagram of a receiver including a sample addition circuit;

FIG. 7 illustrates bit addition and effect on the receiver data signal; and

FIG. 8 is a flowchart of a method of sample addition.

Claims

1. A buffer timing modification system, comprising: a data buffer;a clock signal generator;a switch coupled between the clock signal generator and the data buffer; anda control circuit coupled to the switch and configured to control the switch to interrupt application of a clock signal, generated by the clock signal generator, to the data buffer, thereby preventing the data buffer from running empty when the clock signal has a clock rate that is different from a rate of data received by the data buffer.

2. The system of claim 1, wherein the switch comprises a logic gate.

3. The system of claim 2, wherein the logic gate comprises an AND gate.

4. The system of claim 1, wherein the data buffer, the clock signal generator, the switch, and the control circuit are part of at least one of a wireless receiver, a wireless transmitter, and a wireless transceiver.

5. The system of claim 1, wherein the clock signal generator comprises a crystal-controlled oscillator.

6. The system of claim 1, wherein the clock signal generator is configured to generate the clock signal at a rate of at least one of 12 MHz, a harmonic of 12 MHz, 16.9344 MHz, and a harmonic of 16.9344 MHz.

7. The system of claim 1, wherein the data buffer is configured to receive at least one of audio samples and video samples.

8. A method of modifying buffer timing, comprising: receiving data, having a data rate, at a data buffer;applying a clock signal to the data buffer, wherein the clock signal has a clock rate that is not equal to the data rate;clocking the data through the data buffer under control of the clock signal; andinterrupting the application of the clock signal to the data buffer to prevent the data buffer from running empty.

9. The method as recited in claim 8, wherein the interrupting is based upon the data rate.

10. The method as recited in claim 9, wherein the interrupting comprises interrupting the clock signal for a fixed ratio of clock signal cycles relative to the data rate.

11. The method as recited in claim 10, wherein the interrupting comprises interrupting the clock signal for an average of fourteen clock signal cycles for every one-hundred and twenty-eight samples of the data.

12. The method as recited in claim 8, wherein the interrupting is based upon the clock signal.

13. The method as recited in claim 8, wherein the interrupting comprises interrupting for at least one half-cycle of the clock signal.

14. The method as recited in claim 8, wherein the interrupting comprises interrupting based upon a quantity of the data in the data buffer.

15. The method as recited in claim 8, wherein the interrupting comprises interrupting with an accuracy of at least 1000 parts per million relative to a rate of the data.

16. A sample addition system, comprising: a data buffer;a sample addition circuit coupled to the data buffer;a clock signal generator coupled to the data buffer; anda control circuit coupled to the sample addition circuit and configured to control the sample addition circuit to insert samples into the data buffer, thereby preventing the data buffer from running empty when the clock signal has a clock rate that is different from a rate of data applied to the data buffer.

17. The system of claim 16 wherein the data buffer, the sample addition circuit, and the control circuit are part of at least one of a wireless receiver, a wireless transmitter, and a wireless transceiver.

18. The system of claim 16, wherein the data buffer is configured to receive at least one of audio samples and video samples.

19. The system of claim 16, wherein the control circuit includes a threshold detector coupled to at least one of the data buffer and the sample addition circuit.

20. The system of claim 19, wherein the threshold detector is configured to detect a quantity of data in the data buffer.

21. A method of sample addition, comprising: receiving data, having a data rate, at a data buffer;clocking data through the data buffer under control of a clock signal, wherein the clock signal has a clock rate that is not equal to the data rate; andadding samples to the data buffer to prevent the buffer from running empty.

22. The method as recited in claim 21, wherein the data includes at least one of audio samples and video samples.

23. The method as recited in claim 21, further comprising detecting at least one of a quantity of data in the data buffer, the data rate, and the clock signal rate.

24. The method as recited in claim 23, wherein the adding is based on the detecting.

25. The method as recited in claim 21, wherein the adding is based on at least one of a quantity of data in the data buffer, the data rate, the clock signal rate, a ratio of the clock signal rate to a coder/decoder data input rate, and a ratio of the clock signal rate to the data rate.