Arrangements for synchronising receiver with transmitter

HELECTRICITY H04Electric communication H04LTRANSMISSION OF DIGITAL INFORMATION

H04L7/00Arrangements for synchronising receiver with transmitter

H04L7/0004Initialisation of the receiver H04L7/0008Synchronisation information channels H04L7/0012by comparing receiver clock with transmitter clock H04L7/0016correction of synchronization errors H04L7/002correction by interpolation H04L7/0025interpolation of clock signal H04L7/0029interpolation of received data signal H04L7/0033Correction by delay H04L7/0037Delay of clock signal H04L7/0041Delay of data signal H04L7/0045Correction by a latch cascade H04L7/005Correction by an elastic buffer H04L7/0054Detection of the synchronisation error by features other than the received signal transition H04L7/0058detection of error based on equalizer tap values H04L7/0062detection of error based on data decision error H04L7/0066detection of error based on transmission code rule H04L7/007detection of error based on maximum signal power H04L7/0075with photonic or optical means H04L7/0079Receiver details H04L7/0083taking measures against momentary loss of synchronisation H04L7/0087Preprocessing of received signal for synchronisation H04L7/0091Transmitter details H04L7/0095with mechanical means H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/027extracting the synchronising or clock signal from the received signal spectrum H04L7/0272with squaring loop H04L7/0274with Costas loop H04L7/0276Self-sustaining H04L7/0278Band edge detection H04L7/033using the transitions of the received signal to control the phase of the synchronising-signal-generating means H04L7/0331with a digital phase-locked loop [PLL] processing binay samples H04L7/0332with an integrator-detector H04L7/0334Processing of samples having at least three levels H04L7/0335Gardner detector H04L7/0337Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals H04L7/0338the correction of the phase error being performed by a feed forward loop H04L7/04Speed or phase control by synchronisation signals H04L7/041using special codes as synchronising signal H04L7/042Detectors therefor H04L7/043Pseudo-noise [PN] codes variable during transmission H04L7/044using a single bit H04L7/046using a dotting sequence H04L7/048using the properties of error detecting or error correcting codes H04L7/06the synchronisation signals differing from the information signals in amplitude, polarity, or frequency or length H04L7/065and superimposed by modulation H04L7/08the synchronisation signals recurring cyclically H04L7/10Arrangements for initial synchronisation