Claims
- 1. An EEPROM comprising:
(a) a semiconductor substrate having a surface; (b) a doped memory diffusion region in the semiconductor substrate; (c) a tunnel oxide on said substrate surface and overlying at least a portion of said memory diffusion; (d) a floating gate structure including an extension overlying at least a portion of the tunnel oxide overlying said memory diffusion; and (e) a self-aligned tunnel window defined within at least a portion of the tunnel oxide and having at least two edges defined by the floating gate extension, whereby when a defined voltage is applied to said memory diffusion a tunnel current sufficient to change the state of said EEPROM flows between said memory diffusion and said floating gate structure.
- 2. The EEPROM of claim 1, wherein said tunnel window has two edges defined by edges of the floating gate extension.
- 3. The EEPROM of claim 1, further comprising one or more field oxide regions separated from the tunnel window.
- 4. The EEPROM of claim 3, further comprising a gate oxide located between said one or more field oxide regions and said tunnel window.
- 5. The EEPROM of claim 1, wherein the tunnel window is defined by the intersection of the floating gate extension and the tunnel oxide.
- 6. The EEPROM of claim 5, wherein the floating gate extension and the tunnel oxide are both rectangular shaped.
- 7. The EEPROM of claim 1, wherein said memory diffusion is n-doped.
- 8. An EEPROM comprising:
(a) a semiconductor substrate having a surface; (b) a n-doped memory diffusion region in the semiconductor substrate; (c) a tunnel oxide on said substrate surface, surrounded by an area of gate oxide, and overlying at least a portion of said memory diffusion; (d) a floating gate structure including an extension overlying at least a portion of the tunnel oxide overlying said memory diffusion; (e) a write column electrically connected with a write transistor having as one source/drain region said memory diffusion; (f) a read column electrically connected to a read transistor having as its gate electrode said floating gate; and (g) a self-aligned tunnel window defined by the intersection of the floating gate extension and the tunnel oxide, whereby when a defined voltage is applied to said memory diffusion through said write column a tunnel current sufficient to change the state of said EEPROM flows between said memory diffusion and said floating gate structure and may be read through said read column.
- 9. A method of forming an EEPROM, the method of comprising:
(a) forming a doped memory diffusion region in a semiconductor substrate; (b) forming a tunnel oxide on said substrate and overlying at least a portion of the memory diffusion; and (c) forming a floating gate structure including an extension overlying at least a portion of the tunnel oxide such that the floating gate extension defines at least two edges of a tunnel window within at least a portion of the tunnel oxide, whereby when a defined voltage is applied to said memory diffusion a tunnel current sufficient to change the state of said EEPROM flows between said memory diffusion and said floating gate structure.
- 10. The method of claim 9, wherein forming the floating gate structure includes
(i) depositing a blanket layer of gate electrode material over the semiconductor substrate and tunnel oxide; (ii) masking the blanket layer to define boundaries of the floating gate structure; and (iii) etching the blanket layer to form the floating gate structure.
- 11. The method of claim 9, wherein the etching is performed by a reactive ion etch including a plasma formed from SF6 and Cl2, which selectively etches the blanket layer rather than the tunnel oxide located beyond the edges of the floating gate extension.
- 12. The method of claim 9, wherein forming the floating gate forms two edges of the floating gate extension which define two edges of the tunnel window.
- 13. The method of claim 9, wherein forming the tunnel oxide forms a rectangular shaped tunnel oxide and forming the floating gate structure forms a rectangular shaped floating gate extension intersecting the tunnel oxide, and wherein the intersection of the tunnel oxide and the floating gate extension defines the tunnel window.
- 14. A method of forming an EEPROM, the method of comprising:
(a) generating a p-doped region at a semiconductor substrate surface; and (b) providing a first mask on the substrate surface, said first mask defining boundaries of a field oxide region; and (c) generating a field oxide over the area of the substrate surface unmasked by said first mask; and (d) providing a second mask on said semiconductor substrate, said second mask defining boundaries of a memory diffusion region in at least a portion of the substrate surface free of field oxide; and (e) performing an n-type ion implant over the substrate to create said memory diffusion in the area of the substrate surface unmasked by said second mask; and (f) providing a third mask on the semiconductor substrate, said third mask defining boundaries of a tunnel oxide region over at least a portion of the memory diffusion; and (g) generating a tunnel oxide over the area of the substrate surface unmasked by said third mask; and (h) generating a blanket of a suitable floating gate material over at least a portion of the area defining the intersection of the tunnel oxide and the memory diffusion; and (i) providing a fourth mask on the floating gate material, said fourth mask defining the boundaries of a floating gate, said floating gate comprising an extension overlying at least a portion of the tunnel oxide such that the floating gate defines at least two edges of a tunnel window within at least a portion of the intersection of the tunnel oxide and the memory diffusion; and (j) removing that part of the floating gate material unmasked by the fourth mask.
- 15. The method of claim 14, further comprising removing the masks provided in steps (b), (d), (f) and (i) following steps (c), (e), (g) and (j), respectively.
- 16. The method of claim 14, wherein the memory diffusion is bordered on at least one side by field oxide.
- 17. The method of claim 14, wherein the memory diffusion has a depth of between about 0.4 and 0.8 μm and a concentration of about 1×1018 to 1×1020 cm−3.
- 18. The method of claim 14, further comprising:
(i) generating a gate oxide on the exposed substrate surface following step (e); and (ii) providing a fifth mask, said fifth mask defining the boundaries of a tunnel oxide region; and (iii) removing the gate oxide in the area unmasked by said fifth mask.
- 19. The method of claim 14, wherein the substrate material is silicon, the field oxide and tunnel oxide are silicon dioxide, and the floating gate material is polysilicon.
- 20. The method of claim 14, wherein the tunnel window is separated from the field oxide-induced stress region.
- 21. The method of claim 14, wherein the removal of the blanket of floating gate material in step (j) is performed by a reactive ion etch including a plasma formed from SF6 and Cl2, which selectively etches the blanket layer rather than the tunnel oxide located beyond the edges of the floating gate extension.
Parent Case Info
[0001] This application claims the benefit of the filing date of Provisional Application Serial No. 60/023,725, filed Aug. 8, 1996.
Provisional Applications (2)
|
Number |
Date |
Country |
|
08810642 |
Mar 1997 |
US |
|
60023725 |
Aug 1996 |
US |