Schematic compiler for a multi-format high speed multiplier

Abstract

A multiplier compiler produces a schematic of a high-speed, multi-format multiplier. The compiler receives user information which indicates design preferences. Based on the user information the compiler can select the format of numbers which the multiplier will multiply and/or select a type of adder with which to implement the final adder row of the multiplier. The compiler generates user readable schematics of the multiplier. The schematic displays discrete components of the multiplier arranged in locations which show to the user the flow of logic of the circuit. Additionally, the compiler generates test vectors.

Description

BACKGROUND

The present invention concerns the design of a high-speed, multi-format multiplier, and a multiplier compiler which produces a schematic of the high-speed, multi-format multiplier.

In the design of integrated circuits, synthesis tools and silicon compilers are often used. Based on specifications received from a designer, the synthesis tools, or synthesizers, generate netlists, while the silicon compilers generate "hard" layout of the integrated circuits. Netlists are textual lists of components and connections. Hard layouts show how the components may implemented in silicon. The netlists, once generated, and the hard layout, once generated, are extremely difficult to modify.

Compilers written to produce hardware multipliers have used a variety of algorithms. The goal of each algorithm is to produce a hardware multiplier which has a high circuit density and/or has high performance. The ideal, yet hard to attain, multiplier compiler produces a hardware multiplier which combines high performance while taking up a minimum of space on an integrated circuit.

One solution has been to provide a multiplier compiler which automatically inserts pipeline registers. In one embodiment of such a multiplier compiler, a user specifies the performance rate at which a multiplier is to receive multipliers and multiplicands and produce a product. The multiplier compiler will then produce a multiplier which inserts as many pipeline stages as necessary so that the specified performance rate can be met.

While such a multiplier compiler does facilitate the inclusion of a multiplier in a system which operates at a high frequency, there is no actual performance gain through the multiplier. For example, a combinatorial multiplier with a propagation delay of 50 nanoseconds can be retrofitted to a system with a 30 nanosecond clock rate by the insertion of one pipeline stage. The resultant multiplier will require two 30 nanosecond cycles to complete a multiplication rather than one 50 nanosecond cycle. Thus the overall computational performance of the multiplier is not improved.

An ideal multiplier compiler not only has the flexibility to allow a user to make performance versus chip density trade-offs, but also allows a user flexibility to, in the design of a multiplier, select the format of the multiplier and multiplicand which will be multiplied by the multiplier. Common formats include signed magnitude, unsigned magnitude and two's complement.

Once a multiplier has been included on an integrated circuit that is mass produced, each fabricated integrated circuit is tested to assure that a customer receives working parts. The multiplier is typically tested by applying test vectors to the input of the multiplier, each test vector including a multiplier and a multiplicand. The product for each test vector received from the multiplier is strobed and compared against the correct answer. A product incorrectly calculated by the multiplier indicates flawed circuitry. An integrated circuit containing a multiplier with flawed circuitry is discarded.

One approach to thoroughly test a multiplier is to have a test vector for every combination of multiplier and multiplicand. However, for even moderate size multipliers the required amount of test vectors is impractically high. For example, using such a system, a multiplier which multiplied two eight bit numbers would require 65,536 test vectors. A multiplier which multiplied two ten bit numbers would require 1,048,546 test vectors. Such a large number of test vectors increases the time required to test an integrated circuit, and thus increases the expense of performing testing.

Sets of test vectors may be generated with fewer test vectors in each set, however, it is difficult for a designer of test vectors who is not intimately acquainted with the design of a multiplier to specify an efficient set of test vectors which will thoroughly test a multiplier.

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment of the present invention, a high-speed, multi-format multiplier, and a multiplier compiler which produces a schematic of the high-speed, multi-format multiplier are presented.

In one embodiment of the present invention, a two's complement multiplier includes a plurality of logical gates which are arranged to receive a multiplicand and a multiplier in two's complement format and to generate summands arranged in columns. Adders, organized in rows, each receive summands from a particular column and reduce the number of summands until there is a maximum of two summands per column. Each row of adders reduces a maximum number of summands in each column to a next lower predetermined number stage. In general, the lowest predetermined number stage is two and each predetermined number stage Sj, other than the lowest predetermined number stage, is calculated from a next lower number stage S.sub.j-1 using the following formula: Sj=S.sub.j-1 +int(S.sub.j-1 /2). A final adder row performs a final addition on the summands which remain after the summands have been reduced.

In another embodiment of the present invention it is possible to change the mode of the multiplier. For example, a multiplier may include a mode bit. When the mode bit is in a first state, a plurality of logical gates generates summands for multiplication of unsigned magnitude numbers. When the mode bit is in a second state, the plurality of logical gates generates summands for multiplication of two's complement numbers.

A compiler which is able to generate a multiplier according to the preferred embodiments of the present invention receives from a user information which indicates design preferences. For example, the compiler may receive multiplier selection information, often called a template. Based on the template the compiler selects, for instance, the format of numbers which the multiplier will multiply and the size of the multiplier and multiplicand. For example, the compiler may select a multiplier which will multiply numbers which are in unsigned magnitude format or in two's complement format.

Also the user information may include final adder row information. The compiler uses the final adder row information to select a type of adder with which to implement the final adder row. The final adder row may be implemented, for example, using ripple carry adders, carry look-ahead adders, or carry save adders. The final adder row information may include, for example a direct selection by the user of the type of adder with which to implement the final adder row. Alternately, the final adder row information may include parameters which indicate the desired performance rate of the multiplier. In this case, the compiler selects a type of adder for the final adder row which allows the multiplier to achieve the desired performance rate. A final adder row may account for as much as ninety percent of the total propagation delay of a multiplier; therefore, it is desirable to select the type of adders used in the final adder row based on the user's performance and size constraints.

Additionally, a compiler in accordance with a preferred embodiment of the present invention may generate test vectors. Utilizing the generated test vectors allows for efficient and complete testing of integrated circuits which include multipliers generated by the compiler.

In the preferred embodiment of the present invention, the compiler generates user readable schematics of the multiplier. The schematic displays discrete components of the multiplier arranged in locations which show to the user the flow of logic of the circuit. This facilitates modification and thus customization of the multiplier. Wire segments extending from the discrete components are labelled. The labelling shows the connectivity between the discrete components. Alternately, for example, in less complex designs, wires may be shown between discrete components.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (FIGS. 1A-1B) shows a prior art design of logical AND gates arranged to generate partial products used in a circuit which performs multiplication of unsigned magnitude numbers.

IFG. 2 (FIGS. 2A-2B) shows logical gates arranged to generate summands used in a multiplier which performs multiplication of two's complement numbers in accordance with a preferred embodiment of the present invention.

FIG. 3, FIG. 4 and FIG. 5 show adders arranged to reduce the numbers of summands produced by the logical gates shown in FIG. 2 in accordance with a preferred embodiment of the present invention.

FIG. 6 shows an adder used to perform a final addition on the remaining summands after reduction by the adders shown in FIG. 3, FIG. 4 and FIG. 5 in accordance with a preferred embodiment of the present invention.

FIG. 7 shows a flowchart of a multiplier compiler which generates a high-speed, multi-format multiplier in accordance with the preferred embodiment of the present invention.

FIG. 8 (FIGS. 8A-8B) and FIG. 9 (FIGS. 9A-9B) show a schematic of a high-speed, multi-format multiplier generated by the multiplier compiler described by FIG. 7 in accordance with the preferred embodiment of the present invention.

FIG. 10 shows a block diagram of a tester system in which a tester forwards test vectors to an integrated circuit which includes a multiplier in accordance with a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the preferred embodiment of the present invention, a Wallace tree is modified in order to accommodate the direct multiplication of two's complement numbers. For a general description of a Wallace tree multiplier, see C. S. Wallace, "A Suggestion for Parallel Multipliers", IEEE Transactions on Electronic Computer, Vol. EC-13, February 1964, pp.14-17.

In the first stage of a prior art multiplier, an array of logic gates will produce several rows of partial products. For example, in a five by four multiplier, a five-bit multiplicand A has bits A[4], A[3], A[2], A[1], A[O] where bit A[4] is the high order bit and where bit A[0] is the low order bit, and a four-bit multiplier has bits B[3], B[2], B[1], B[0] where bit B[3] is the high order bit and where bit B[0] is the low order bit. In a typical prior art multiplier, an array of logical AND gates 11 through 30, shown in FIG. 1, are used to logically AND each bit of multiplicand A with each bit of multiplier B in order to generate a plurality of partial products.

The partial products are organized in rows. For example, a first row of partial product bits includes partial product bits labelled C.sub.O [O], C.sub.1 [0], C.sub.2 [0], C.sub.3 [0] and C.sub.4 [0]. A second row of partial product bits includes partial product bits labelled C.sub.1 [1], C.sub.2 [1], C.sub.3 [1], C.sub.4 [1] and C.sub.5 [0]. A third row of partial product bits includes partial product bits labelled C.sub.2 [2], C.sub.3 [2], C.sub.4 [2], C.sub.5 [1] and C.sub.6 [0]. A fourth row of partial product bits includes partial product bits labelled C.sub.3 [3], C.sub.4 [3], C.sub.5 [2], C.sub.6 [1] and C.sub.7 [0]. Each of the partial product bits are also arranged into column 1 through column 7 as shown. In order to determine the value which each partial product bit represents, the partial product bit may be multiplied by two raised to the power represented by the column number. That is a partial product bit C.sub.5 [0] which is in column five represents a value of C.sub.5 [0] times 2.sup.5.

It has been shown that using an array similar to array of logical AND gates 11 through 26 allows the production of partial products useful in a multiplier which performs the multiplication of two's complement numbers. See, for example, Baugh, C. R. and Wooley, B. A., "A Two's Complement Parallel Array Multiplication Algorithm", IEEE Trans. Comp., Vol. C-22, No. 1-2, Dec. 1973, pp. 1045, 1047; or Kai Hwang, "Computer Arithmetic: Principles, Architecture and Design". New York: John Wiley & Sons, 1979, pp. 179-183.

As may be understood from these references, in general, for two's complement multiplication of a multiplicand A having n bits and a multiplier B having m bits, the partial products vary from standard partial products in the following ways. First, each bit of multiplier B, except the high order bit (B.sub.m-1) is inverted before a logical AND is performed with the high order bit (A.sub.n-1) of the multiplicand. Similarly, each bit of multiplicand A, except the high order bit (A.sub.n-1) is inverted before a logical AND is performed with the high order bit (B.sub.m-1) of the multiplier. Second, additional partial product bits are added as follows: A bit equal in value to high order bit A.sub.n-1 is added to column n-1. A bit equal in value to high order bit B.sub.m-1 is added to column m-1. A bit equal in value to the inverse of high order bit A.sub.n-1 is added to column m+n-2. A bit equal in value to the inverse of high order bit B.sub.m-1 is added to column m+n-2. A bit equal in value to 1 is added to column m+n-1.

For example, FIG. 2 shows how the logical AND gate array shown in FIG. 1 may be modified to accommodate the generation of partial product bits for two's complement multiplication. A logic "1" is used directly to generate a partial product bit C.sub.8 [0].

An inverter 41 is used to invert multiplier bit B[0] before logic gate 15 performs a logic AND on multiplier bit B[O] and multiplicand bit A[4]. An inverter 42 is used to invert multiplier bit B[1] before logic gate 20 performs a logic AND on multiplier bit B[1] and multiplicand bit A[4]. An inverter 43 is used to invert multiplier bit B[2] before logic gate 25 performs a logic AND on multiplier bit B[2] and multiplicand bit A[4].

An inverter 44 is used to invert multiplicand bit A[0] before logic gate 26 performs a logic AND on multiplicand bit A[0] and multiplier bit B[3]. An inverter 45 is used to invert multiplicand bit A[1] before logic gate 27 performs a logic AND on multiplicand bit A[1] and multiplier bit B[3]. An inverter 46 is used to invert multiplicand bit A[2] before logic gate 28 performs a logic AND on multiplicand bit A[2] and multiplier bit B[3]. An inverter 47 is used to invert multiplicand bit A[3] before logic gate 29 performs a logic AND on multiplicand bit A[3] and multiplier bit B[3].

The multiplicand bit A[4] is used to directly generate a partial product bit C.sub.4 [4]. The multiplier bit B[3] is used to directly generate a partial product bit C.sub.3 [4]. An inverter 48 inverts multiplicand bit A[4] to generate a partial product bit C.sub.7 [1]. An inverter 49 inverts multiplier bit B[3] to generate a partial product bit C.sub.7 [2].

Once the partial products are generated, a Wallace tree may be used to sum them. The present invention differs from the prior art, however, in that the additional partial product bits generated during the multiplication of two's complement numbers are included in the Wallace tree.

In a Wallace tree, each partial product is not dealt with as a whole, but rather each partial product bit, referred to as a summand, is handled individually. The Wallace tree employs rows of adders, each row of adders reducing the maximum number of summands in a column, until there is a maximum of two summands in each column. The reduction may be done in a variety of ways.

In the preferred embodiment of the present invention, full adders and half adders may be used to reduce the maximum number of summands in a column to a next lower predetermined stage. In the preferred embodiment of the present invention, the predetermined stages are 2, 3, 4, 6, 9, 13, 19, 28, 42, 63 . . . In general, a next higher stage S.sub.j+1 may be calculated from an immediately lower stage S.sub.j by the formula:

S.sub.j+1 =S.sub.j +int(S.sub.j /2)

For example, in the example given in FIG. 2, there is one summand in column 0, there are two summands in column 1, there are three summands in column 2, there are five summands in column 3, there are five summands in column 4, there are three summands in column 5, there are two summands in column 6, there are three summands in column 7 and there is one summand in column 8. The maximum number of summands in a column is five summands in column 3 and in column 4. The next lower predetermined stage from five is four (recall the stages are 2, 3, 4, 6, 9, 13, 19, 28, 42, 63 . . . ). Therefore in every column in which the number of summands is greater than four, the first row of adders reduces the number of summands to four.

FIG. 3 shows a row of adders which performs the reduction. A half adder 111 receives summand C.sub.3 [0] and summand C.sub.3 [1] from column 3 and produces a summand C.sub.3 [5] which is included in column 3 and a summand C.sub.4 [5] which is included in column 4. Column 3 now has four summands while column 4 has six summands.

A full adder 112 receives summand C.sub.4 [0], summand C.sub.4 [1], and summand C.sub.4 [2] from column 4 and produces a summand C.sub.4 [6] which is included in column 4 and a summand C.sub.5 [3] which is included in column 5. Column 4 now has four summands and column 5 has four summands. Since now the maximum summands per column is four, no further adders are required in this row.

After the first row of adders, shown in FIG. 3, there is one summand in column 0, there are two summands in column 1, there are three summands in column 2, there are four summands in column 3, there are four summands in column 4, there are four summands in column 5, there are two summands in column 6, there are three summands in column 7 and there is one summand in column 8. The maximum number of summands in a column is four summands in column 3, in column 4 and in column 5. The next lower predetermined stage from four is three. Therefore in every column in which the number of summands is greater than three, the second row of adders reduces the number of summands to three.

FIG. 4 shows a row of adders which performs the reduction. A half adder 121 receives summand C.sub.3 [2] and summand C.sub.3 [2] from column 3 and produces a summand C.sub.3 [6] which is included in column 3 and a summand C.sub.4 [7] which is included in column 4. Column 3 now has three summands while column 4 has five summands.

A full adder 122 receives summand C.sub.4 [3], summand C.sub.4 [4], and summand C.sub.4 [5] from column 4 and produces a summand C.sub.4 [8] which is included in column 4 and a summand C.sub.5 [5] which is included in column 5. Column 4 now has three summands and column 5 has five summands.

A full adder 123 receives summand C.sub.5 [0], summand C.sub.5 [1], and summand C.sub.5 [2] from column 5 and produces a summand C.sub.5 [5] which is included in column 5 and a summand C.sub.6 [2] which is included in column 6. Column 5 now has three summands and column 6 has three summands. Since now the maximum summands per column is three, no further adders are required in this row.

After the second row of adders, shown in FIG. 4, there is one summand in column 0, there are two summands in column 1, there are three summands in column 2, there are three summands in column 3, there are three summands in column 4, there are three summands in column 5, there are three summands in column 6, there are three summands in column 7 and there is one summand in column 8. The maximum number of summands in a column is three summands in column 2, in column 3, in column 4, in column 5, in column 6 and in column 7. The next lower predetermined stage from three is two. Therefore in every column in which the number of summands is greater than two, the third row of adders reduces the number of summands to two.

FIG. 5 shows a row of adders which performs the reduction. A half adder 131 receives summand C.sub.2 [0] and summand C.sub.2 [1] from column 2 and produces a summand C.sub.2 [3] which is included in column 2 and a summand C.sub.3 [7] which is included in column 3. Column 2 now has two summands while column 3 has four summands.

A full adder 132 receives summand C.sub.3 [4], summand C.sub.3 [5], and summand C.sub.3 [6] from column 3 and produces a summand C.sub.3 [8] which is included in column 3 and a summand C.sub.4 [9] which is included in column 4. Column 3 now has two summands and column 4 has four summands.

A full adder 133 receives summand C.sub.4 [6], summand C.sub.4 [7], and summand C.sub.4 [8] from column 4 and produces a summand C.sub.4 [10] which is included in column 4 and a summand C.sub.5 [6] which is included in column 5. Column 4 now has two summands and column 5 has four summands.

A full adder 134 receives summand C.sub.5 [3], summand C.sub.5 [4], and summand C.sub.5 [5] from column 5 and produces a summand C.sub.5 [7] which is included in column 5 and a summand C.sub.6 [3] which is included in column 6. Column 5 now has two summands and column 6 has four summands.

A full adder 135 receives summand C.sub.6 [0], summand C.sub.6 [11], and summand C.sub.6 [2] from column 6 and produces a summand C.sub.6 [4] which is included in column 6 and a summand C.sub.7 [3] which is included in column 7. Column 6 now has two summands and column 7 has four summands.

A full adder 136 receives summand C.sub.7 [0], summand C.sub.7 [1], and summand C.sub.7 [2] from column 7 and produces a summand C.sub.7 [4] which is included in column 7 and a summand C.sub.8 [1] which is included in column 8. Column 7 now has two summands and column 8 has two summands.

After the third set of adders, shown in FIG. 5, there is one summand in column 0, and there are two summands in column 1 through column 8. An adder is used to sum the summands.

For example, FIG. 6 shows a ripple carry adder which may be used to perform the addition. A product bit P.sub.0 is generated by summand C.sub.0 [0]. A half adder 141 receives summand C.sub.1 [O] and C.sub.1 [1]. Half adder 141 produces a product bit P.sub.1 and a carry out. A full adder 142 receives summand C.sub.2 [2], summand C.sub.2 [3] and the carry out from half adder 141. Full adder 142 produces a product bit P.sub.2 and a carry out. A full adder 143 receives summand C.sub.3 [7], summand C.sub.3 [8] and the carry out from full adder 142. Full adder 143 produces a product bit P.sub.3 and a carry out. A full adder 144 receives summand C.sub.4 [9], summand C.sub.4 [10] and the carry out from full adder 143. Full adder 144 produces a product bit P.sub.4 and a carry out. A full adder 145 receives summand C.sub.5 [6], summand C.sub.5 [7] and the carry out from full adder 144. Full adder 145 produces a product bit P.sub.5 and a carry out. A full adder 146 receives summand C.sub.6 [3], summand C.sub.6 [4] and the carry out from full adder 145. Full adder 146 produces a product bit P.sub.6 and a carry out. A full adder 147 receives summand C.sub.7 [3], summand C.sub.7 [4] and the carry out from full adder 146. Full adder 147 produces a product bit P.sub.7 and a carry out. A full adder 148 receives summand C.sub.8 [0], summand C.sub.8 [1] and the carry out from full adder 147. Full adder 148 produces a product bit P.sub.8. The carry out from full adder 148 is not used.

In accordance with the preferred embodiment of the present invention, a circuit compiler may be used to generate the circuit described above for placement onto an integrated circuit. The output of the circuit compiler is a schematic rather than a "netlist" as is typical for prior art synthesizers and rather than a "hard layout" as is typical for prior art silicon compilers. The schematic output renders the logic of the multiplier more easily understandable to a designer and facilitates designer modifications. The schematic includes discrete components, for example, logic gates, half adders, full adders, etc. The discrete components are arranged in locations which show to the user the flow of logic of the circuit. This facilitates modification and thus customization of the multiplier. Wire segments extending from the discrete components are labelled. The labelling shows the connectivity between the discrete components. Alternately, for example, in less complex designs, wires may be shown between discrete components.

FIG. 7 shows a simplified block diagram of such a compiler program. In a step 72 the compiler program selects parameters for the multiplier. This selection may be based, for example, on parameters which were sent to the compiler program on start-up, or on information given by a user in response to prompting by the compiler program. These parameters may include, for example, a specification as to the format of the numbers to be multiplied, e.g., whether the multiplier will be multiplying unsigned magnitude numbers, two's complement numbers, or both. The parameters also may include the number of bits in the multiplier and the number of bits in the multiplicand.

In a step 73, the compiler program selects the type of adder which performs the final addition. This selection may be based, for example, on parameters which were sent to the compiler program on start-up, or on information given by a user in response to prompting by the compiler program. The user may directly indicate what type of adder to use. Alternately, the user may give the compiler other information, for instance the performance rate required for the multiplier. From this information, the compiler can determine the most suitable adder. In general, when conserving space on an integrated circuit is the most important consideration, a ripple carry adder will be used. When speed of the multipliers is of preeminent importance, adders such as carry-look ahead adders or carry save adders may be used.

In a step 74, the compiler program builds an array of AND gates which generate the summands discussed above. The array of AND gates is, for example, similar to the arrays shown in FIG. 2. Also, for some integrated circuits technologies, better performance is obtained by replacing some or all the AND gates with logical equivalents, for example NOR gates with inverted inputs.

In a step 75, the compiler program builds rows of adders which reduce the summands. Each adder within a row of adders, reduce the number of summands in a particular row. The rows of adders may include full adders which reduce three inputs to a sum bit and a carry bit. The rows of adders may also include half adders. Half adders receive two inputs and generate a sum bit and a carry bit. Alternately, other adder technologies may be utilized. For instance, a seven bit adder, e.g., a seven-to-three encoder, may be used in the reduction of the number of summands.

In a step 76, the compiler program builds a final adder based on the selection made in step 73. In a step 77, the compiler program displays a schematic of the multiplier. In a step 78, test vectors for the multiplier are generated.

FIG. 8 and FIG. 9 show an example of a schematic display generated by a compiler program according to the preferred embodiment of the present invention. In FIG. 8 and FIG. 9, when a mode input 190 is equal to zero, the multiplier implements the multiplication of a five bit multiplicand A by a four bit multiplicand B, both in unsigned magnitude format. When mode input 190 is equal to one, the multiplier implements the multiplication of five bit multiplicand A by four bit multiplicand B, both in two's complement format.

In FIG. 8, the array of AND gates in the generated multiplier is implemented using NOR gates. In order to invert the inputs to the NOR gates, a series of inverters 182 inverts multiplicand bits A[4], A[3], A[2], A[1], A[0] to produce inverted multiplicand bits NA[4], NA[3], NA[2], NA[1], NA[0]. Similarly, a series of inverters 183 inverts multiplier bits B[3], B[2], B[1], B[0] to produce inverted multiplier bits NB[3], NB[2], NB[1], NB[0].

Logical NOR gates 111-130 correspond to the Logical AND gates 11-30, shown in FIG. 1 and FIG. 2. Logical XNOR gates 191, 192, 193, 194, 195, 196 and 197 have been added to facilitate the multiplication of both two's complement numbers and unsigned magnitude numbers. Mode bit 190 is inverted by an inverter 181 before being connected to logical XNOR gates 191-197. When mode input 190 is one, logical NOR gate 115 receives multiplier bit B[0], logical NOR gate 120 receives multiplier bit B[1] and logical NOR gate 125 receives multiplier bit B[2]. Similarly, when mode input 190 is one, logical NOR gate 126 receives multiplicand bit A[0], logical NOR gate 127 receives multiplicand bit A[1], logical NOR gate 128 receives multiplicand bit A[2] and logical NOR gate 129 receives multiplicand bit A[3].

When mode input 190 is zero, logical NOR gate 115 receives the inverse of multiplier bit B[0], logical NOR gate 120 receives the inverse of multiplier bit B[1] and logical NOR gate 125 receives the inverse of multiplier bit B[2]. Similarly, when mode input 190 is zero, logical NOR gate 126 receives the inverse of multiplicand bit A[0], logical NOR gate 127 receives the inverse of multiplicand bit A[1], logical NOR gate 128 receives the inverse of multiplicand bit A[2] and logical NOR gate 129 receives the inverse of multiplicand bit A[3].

In FIG. 9, a full adder 211, with an input 260 connected to a ground (VSS) 260, corresponds to half adder 111 shown in FIG. 3. A logical AND gate 251 forwards the extra summand bit B[3] to full adder 211 when mode input bit 190 is equal to one. A full adder 212 corresponds to full adder 112. A logical AND gate 252 forwards the extra summand bit A[4] to full adder 211 when mode input bit 190 is equal to one.

A full adder 221, a full adder 222 and a full adder 223 correspond respectively to full adder 121, full adder 122 and full adder 123 shown in FIG. 4. A full adder 231, a full adder 232, a full adder 233, a full adder 234, a full adder 235 and a full adder 236 correspond respectively to full adder 131, full adder 132, full adder 133, full adder 34, full adder 135 and full adder 136 shown in FIG. 5. A logical AND gate 253 forwards the extra summand bit NA[4] to full adder 236 when mode input bit 190 is equal to one. A logical AND gate 254 forwards the extra summand bit NB[3] to full adder 236 when mode input bit 190 is equal to one.

The final addition of columns is implemented by a two-bit adder 241, a two-bit adder 243, a two-bit adder 245 and a two-bit adder 247. When it is essential to increase the speed of the multiplier, in step 73 the multiplier compiler selects two-bit adders 241, 243, 245 and 247 to be carry look-ahead adders or carry save adders. Otherwise, the multiplier compiler may select two-bit adders 241, 243, 245 and 247 to be ripple carry adders. Alternately, the multiplier compiler may select other adder configurations such as eight-bit or sixteen-bit adders.

In order to allow thorough testing of a multiplier in an integrated circuit with a minimum of non-zero test vectors, the multiplier compiler generates a set of non-zero test vectors. For each test vector, a value for the multiplicand and a value for the multiplier is given. These are entered into the multiplier and the answer is checked. In addition to the non-zero test vectors, at least one test vector should be included where the multiplier and the multiplicand are both equal to zero.

The following non-zero test vectors are generated as described in table 1 below:

TABLE 1______________________________________Test Vector 1:Multiplicand: all bits are 1.Multiplier: low order bit is 1, remaining bits are 0.Test Vector 2:Multiplicand: bits alternate between 0 and 1, low order bit is 0.Multiplier: bits alternate between 1 and 0, low order bit is 1.Test Vector 3:Multiplicand: all bits are 1.Multiplier: all bits are 1.Test Vector 4:Multiplicand: bits alternate between 0 and 1, low order bit is 0.Multiplier: bits alternate between 0 and 1, low order bit is 0.Test Vector 5:Multiplicand: bits alternate between 1 and 0, low order bit is 1.Multiplier: bits alternate between 1 and 0, low order bit is 1.Remaining Test Vectors: Generating "walking ones" test vectors. For each bit position of the multiplicand and the multiplier a test vector is generated so that corresponding bits of the multiplicand and multiplier are 1 and the remaining bits are 0. By corresponding bits is meant bits in the same bit position. When there is not a bit in the multiplier (or the multiplicand) which is in the same bit position as a bit in the multiplicand (or the multiplier) because the multiplicand (or multiplier) is larger than the multiplier (or multiplicand), what is meant by a corresponding bit of such a bit in the multiplicand (or multiplier) is the high order bit in the multiplier (or multiplicand).______________________________________

In order to toggle all bits within the multiplier, the value of the multiplier and the value of the multiplicand must be set to zero between one or more of the test vectors. For example, in Table 2 below, there is shown sample hexadecimal values for test vectors, both non-zero test vectors and test vectors of all zeros, for a ten by eight multiplier.

TABLE 2______________________________________Multiplicand Multiplier______________________________________000 003ff 01000 002aa 55000 003ff ff000 002aa aa000 00155 55000 00001 01002 02004 04008 08010 10020 20040 40080 80100 80200 80______________________________________

FIG. 10 shows a tester 301 which forwards test vectors to an integrated circuit 300 through a tester interface 302. Integrated circuit 300 includes a multiplier which performs multiplication of the test vectors. An product of the multiplication is returned to the tester through tester interface 302. Tester 301 checks the product to assure the multiplication was performed without error.

A program implementing a compiler in accordance to the preferred embodiment is attached hereto as Appendix A. ##SPC1##

Claims

1. An integrated circuit which implements the multiplication of a multiplicand and a multiplier in two's complement format, the integrated circuit comprising:

a plurality of logical gates, arranged to receive the multiplicand and the multiplier and to generate summands for two's complement multiplication, the summands arranged in columns;

a reduction means, coupled to the plurality of logical gates, for reducing the summands generated by the plurality of logical gates so there is a maximum of two summands in each column, the reduction means including a plurality of adders arranged in rows so that each row of adders reduces a maximum number of summands in each column to a next lower predetermined number stage; and,

a final adder row which performs a final addition on summands remaining after the summands have been reduced by the reduction means.

2. An integrated circuit as in claim 1 wherein a lowest predetermined number stage is two and wherein a predetermined number stage S.sub.j, other than the lowest predetermined number stage, is calculated by a next lower number stage S.sub.j-1 using a formula: S.sub.j =S.sub.j-1 +int(S.sub.j-1 /2).

3. A method for performing multiplication of a multiplicand by a multiplier, the multiplicand and the multiplier being in two's complement numbers on an integrated circuit, the method comprising the steps of:

(a) receiving, by a plurality of logical gates, the multiplicand and the multiplier;

(b) generating, by the plurality of logical gates, summands for two's complement multiplication, the summands arranged in columns;

(c) reducing the summands generated by the plurality of logical gates so there is a maximum of two summands in each column, the reduction being done by a plurality of adders arranged in rows so that each row of adders reduces a maximum number of summands in each column to a next lower predetermined number stage; and,

(d) performing a final addition on summands remaining after the summands have been reduced.

4. A method as in claim 3 wherein, in step (c), a lowest predetermined number stage is two and wherein a predetermined number stage S.sub.j, other than the lowest predetermined number stage, is calculated by a next lower number stage S.sub.j-1 using a formula: S.sub.j =S.sub.j-1 +int(S.sub.j-1 /2)

5. An integrated circuit which implements the multiplication of a multiplicand and a multiplier, the integrated circuit comprising:

a plurality of logical gates, arranged to receive the multiplicand and the multiplier and to generate summands, the summands arranged in columns;

a reduction means, coupled to the plurality of logical gates, for reducing the summands generated by the plurality of logical gates so there is a maximum of two summands in each column, the reduction means including a plurality of adders arranged in rows so that each row of adders reduces a maximum number of summands in each column to a next lower predetermined number stage;

an adder which performs a final addition on summands remaining after the summands have been reduced by the reduction means; and,

mode changing means, coupled to the plurality of logical gates, for, when a mode bit is in a first state, causing the plurality of logical gates to generate summands for multiplication of unsigned magnitude numbers, and when the mode bit is in a second state, causing the plurality of logical gates to generate summands for multiplication of two's complement numbers.

6. An integrated circuit as in claim 5 wherein a lowest predetermined number stage is two and wherein a predetermined number stage S.sub.j, other than the lowest predetermined number stage, is calculated by a next lower number stage S.sub.j-1 using a formula: S.sub.j =S.sub.j-1 +int(S.sub.j-1 /2).