Patent Application
20240105859
The present patent application claims the priority of Japanese patent application No. 2022/153043 filed on Sep. 26, 2022, and the entire contents of Japanese patent application No. 2022/153043 are hereby incorporated by reference.
The present invention relates to a Schottky barrier diode.
A Schottky barrier diode is known which is provided with a trench MOS structure and a semiconductor layer formed of a Ga2O3-based semiconductor as a wide-bandgap semiconductor (see Patent Literature 1).
The Schottky barrier diode described in Patent Literature 1 has a high-withstand voltage and low-loss characteristics because of using the semiconductor layer formed of the Ga2O3-based semiconductor as the wide-bandgap semiconductor, and, in addition, it can have a higher withstand voltage because of having the trench MOS structure without increasing the resistance of the semiconductor layer.
It is an object of the invention to provide a Schottky bather diode with a trench structure that has an even higher withstand voltage than the known art.
An aspect of the invention provides a Schottky barrier diode defined in (1) to (7) below.
Herein, “impurity of first (or second) conductivity type” is intended to mean an impurity that can provide a semiconductor of the first (or second) conductivity type when a pure semiconductor is doped with the impurity.
According to the invention, it is possible to provide a Schottky bather diode with a trench structure that has an even higher withstand voltage than those of the known art.
In
The Schottky barrier diode 1 includes the n-type semiconductor layer 11 formed of a gallium oxide-based semiconductor and having the trench 111 defining the mesa portions 112 on an upper surface, a high-resistance region 14 that is provided under the trench 111 of the semiconductor layer 11 and contains a p-type impurity, an insulating film 15 that is provided so as to cover at least a bottom surface among inner surfaces of the trench 111, the anode electrode 16 that is provided on the semiconductor layer 11 through the insulating film 15 and connected to the mesa portions 112, and a cathode electrode 17 provided directly or through another layer on a lower surface of the semiconductor layer 11. Herein, “p-type (or n-type) impurity” is intended to mean an impurity that can provide a semiconductor of p- (or n-) conductivity type when a pure semiconductor is doped with the impurity.
The “upper surface” of the semiconductor layer 11 is one of principal surfaces of the semiconductor layer 11 and is a surface on the upper side in
The Schottky barrier diode 1 preferably includes the guard ring 18 to increase resistance to surge currents, as shown in
In
The mesa portion 112 of the semiconductor layer 11 and the anode electrode 16 form a Schottky junction, and the Schottky barrier diode 1 uses the rectifying properties of this Schottky junction. In the Schottky barrier diode 1, a potential barrier at an interface between the anode electrode 16 and the semiconductor layer 11 as viewed from the semiconductor layer 11 is lowered by applying forward voltage between the anode electrode 16 and the cathode electrode 17 (positive potential on the anode electrode 16 side), allowing a current to flow from the anode electrode 16 to the cathode electrode 17.
On the other hand, when reverse voltage is applied between the anode electrode 16 and the cathode electrode 17 (negative potential on the anode electrode 16 side), the current does not flow due to the Schottky barrier. At this time, since depletion layers spread toward the inside of the mesa portions 112 from the interfaces between the anode electrode 16 and the mesa portions 112 and between the insulating film 15 and the mesa portions 112 and close channels, leakage current is efficiently suppressed.
Typically, the Schottky barrier diode 1 includes an n-type semiconductor substrate 10 as a base for epitaxial growth of the semiconductor layer 11, and the lower surface of the semiconductor layer 11 is in contact with the semiconductor substrate 10, as shown in
The semiconductor substrate 10 is formed of a single crystal of an n-type gallium oxide-based semiconductor containing a group IV element such as Si or Sn as a donor. A donor concentration in the semiconductor substrate 10 is, e.g., not less than 1.0×1016 cm−3 and not more than 1.0×1019 cm−3. A thickness of the semiconductor substrate 10 is, e.g., not less than 400 μm and not more than 700 μm.
The semiconductor layer 11 is formed of a single crystal of an n-type gallium oxide-based semiconductor containing a group IV element such as Si or Sn as a donor. A donor concentration in the semiconductor layer 11 is lower than the donor concentration in the semiconductor substrate 10 and is, e.g., not less than 1.0×1016 cm−3 and not more than 5.0×1016 cm−3. A thickness of the semiconductor layer 11 is, e.g., not less than 5 μm and not more than 15 μm. The semiconductor layer 11 is composed of, e.g., an epitaxial film epitaxially grown on the semiconductor substrate 10.
The gallium oxide-based semiconductor is Ga2O3 or is Ga2O3 doped with one or both of Al and In, and has a composition represented by (GaxAlyIn(1-x-y))2O3 (0<x≤1, 0≤y<1, 0<x+y≤1). Ga2O3 has a wider band gap when doped with Al and a narrower band gap when doped with In. The single crystal of the gallium oxide-based semiconductor mentioned above typically has a β-crystal structure. For example, Ga2O3, which is a typical example of gallium oxide-based semiconductor, has a bandgap energy of 4.5 to 4.9 eV and a breakdown field strength of about 8.0 MV/cm.
When the thickness of the semiconductor layer 11 is designed so that an electric field, which is generated in each part when a reverse voltage equal to the design withstand voltage is applied to the Schottky barrier diode 1, is smaller than the breakdown field, the deeper the trench 111, the lower the electric field at the Schottky interfaces between the anode electrode 16 and the mesa portions 112 when reverse voltage is applied. However, if the trench 111 is too deep, electrical resistance between the anode electrode 16 and the cathode electrode 17 of the Schottky barrier diode 1 increases. Thus, the depth of the trench 111 is set to, e.g., not less than 1 μm and not more than 3 μm.
The narrower the width of the trench 111, the lower the conduction loss but the more difficult it is to manufacture, hence, the width of the trench 111 is set to, e.g., not less than 0.5 μm and not more than 2.0 μm. The narrower the width of the mesa portion 112, the lower the electric field strength in the mesa portion 112 but the more difficult it is to manufacture, hence, the width of the mesa portion 112 is set to, e.g., not less than 0.5 μm and not more than 2.0 μm.
The planar pattern of the mesa portions 112 is, e.g., a lines-and-spaces pattern as shown in
The field strength in the Schottky barrier diode 1 is affected by the width of the mesa portions 112 and the depth of the trench 111, etc., described above but is hardly affected by the planar patterns of the trench 111 and the mesa portions 112. Thus, the planar patterns of the trench 111 and the mesa portions 112 on the semiconductor layer 11 are not specifically limited.
The high-resistance region 14 is a region whose resistance is increased by implanting a p-type impurity such as nitrogen (N) that forms a deep acceptor level in the gallium oxide-based semiconductor. The high-resistance region 14 acts as an electric field relaxation layer and can improve withstand voltage of the Schottky barrier diode 1.
A depth of the high-resistance region 14 is, e.g., not less than 0.1 μm and not more than 0.5 μm, and a p-type impurity concentration, i.e., an acceptor concentration, in the high-resistance region 14 is, e.g., not less than 5.0×1017 cm−3 and not more than 5.0×1018 cm−3. To effectively exert the electric field relaxation effect of the high-resistance region 14, it is preferable to satisfy a relationship W×Nd<D×Na, where W is a width of a depletion layer formed in the semiconductor layer 11 from the bottom surface of the trench 111 in the depth direction when a reverse voltage is applied, Nd is a donor concentration in the high-resistance region 14, D is a depth of the high-resistance region 14 from the bottom surface of the trench 111, and Na is an acceptor concentration in the high-resistance region 14.
The insulating film 15 is preferably provided so as to cover not only the bottom surface among the inner surfaces (i.e., bottom and side surfaces) of the trench 111 but also side surfaces (which are shared by the trenches 111) of the mesa portions 112, as shown in
The insulating film 15 is, e.g., a SiO2 film or a stacked film in which an Al2O3 film is stacked on a SiO2 film. When the insulating film 15 is a stacked film in which an Al2O3 film is stacked on a SiO2 film, e.g., a thickness of the SiO2 film is not less than 50 nm and not more than 200 nm and a thickness of the Al2O3 film is not less than 10 nm and not more than 30 nm.
The anode electrode 16 is in contact with the insulating film 15 and the mesa portions 112 exposed from the insulating film 15. The anode electrode 16 typically includes a film-shaped first layer 161 coveting the insulating film 15 and the upper portions of the mesa portions 112 exposed from the insulating film 15, and a second layer 162 on the first layer 161, as shown in
To relax electric field concentration at an end portion of the anode electrode 16 in a planar direction, the anode electrode 16 is preferably arranged such that the end portion in the planar direction overlies a field insulating film 19. In this case, the field insulating film 19 is provided so as to cover the bottom surface of the trench 111 in the vicinity a terminal end portion thereof. The field insulating film 19 is, e.g., a silicon oxide film. A thickness of the field insulating film 19 is, e.g., not less than 400 nm and not more than 2000 nm.
The anode electrode 16 is in ohmic contact with the guard ring 18 and forms a built-in p-n diode with the semiconductor layer 11. Thus, when a surge current flows through the Schottky barrier diode 1, part of the surge current can flow through the built-in p-n diode and thermal destruction of the Schottky barrier diode 1 due to the surge current can be prevented.
When the Schottky barrier diode 1 includes semiconductor substrate 10, the cathode electrode 17 is in ohmic contact with the semiconductor substrate 10. When the Schottky barrier diode 1 does ml include the semiconductor substrate 10 and the cathode electrode 17 is directly connected to the semiconductor layer 11, the cathode electrode 17 is in ohmic contact with the semiconductor layer 11. The cathode electrode 17 has, e.g., a stacked structure in which an Au film is stacked on a Ti film. In this case, a film formed of Ni or Mo, etc., may be provided as a barrier metal between the Ti film and the Au film.
(Method for Manufacturing the Schottky Barrier Diode)
An example of a method for manufacturing the Schottky barrier diode 1 will be described below.
Firstly, as shown in
The NiO film 180 is formed to a thickness of not less than 50 nm and not more than 200 nm by sputtering and is then processed into the pattern shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
The insulating film 15 is formed to a thickness of not less than 50 nm and not more than 200 nm by CVD. An Al2O3 film may additionally be formed to a thickness of not less than 10 nm and not more than 30 nm on the TEOS film by ALD (Atomic Layer Deposition) so that the stacked film composed of the TEOS film and the Al2O3 film is provided as the insulating film 15. In this case, the Al2O3 film acts as an etching stopper film in an etch-back step described next.
Next, as shown in
The resist etch-back is performed by, e.g., fluorine-based dry etching using a fluorine-based etching gas such as CF4 gas, and the etching is finished when the resist on the mesa portions 112 and the guard ring 18 is etched. When the insulating film 15 is a single layer of TEOS film, the insulating film 15 on the mesa portions 112 and the guard ring 18 is also etched at this time. When the insulating film 15 is a stacked film composed of a TEOS film and an Al2O3 film, the Al2O3 film acts as an etching stopper, hence, e.g., the Al2O3 film is etched with an alkaline solution such as TMAH (tetramethylammonium hydroxide) solution and the TEOS film thereunder is etched with a chemical solution containing fluorine, such as hydrofluoric acid. After removing the insulating film 15 on the mesa portions 112 and the guard ring 18, the remaining resist is removed. After that, heat treatment at a temperature of not less than 400° C. and not more than 500° C. is performed as annealing for etching damage recovery.
Next, after cleaning the wafer with a mixture solution of pure water, hydrogen peroxide and sulfuric acid, a stacked film composed of a Mo film, a Ni film and an Au film, etc., is formed to a thickness of not less than 50 nm and not more than 500 nm as the first layer 161 of the anode electrode 16 by vapor deposition, as shown in
Next, as shown in
Subsequently, after protecting the wafer front surface with a resist, the TEOS film formed on the wafer back surface, i.e., the lower surface of the semiconductor substrate 10, is removed using, e.g., a chemical solution containing fluorine, such as hydrofluoric acid. Then, after removing the resist, a stacked film composed of a Ti film and an Au film is formed as the cathode electrode 17 on the lower surface of the semiconductor substrate 10. A Ni film or a Mo film may be provided as a barrier metal between the Ti film and the Au film. When a stacked film composed of a TEOS film and an Al2O3 film is used as the insulating film 15, the insulating film removal step before forming the cathode electrode 17 can be omitted since the insulating film formed on the wafer back surface has already been removed by wet etching in the resist etch-back step described above.
In this modification, firstly, the steps up to the formation of the trench 111 shown in
Next, as shown in
Next, as shown in
Next, as shown in
After that, the resist 54 is removed, and the step of forming the field insulating film 19 and the insulating film 15 shown in
By removing the SiO2 film 51 after forming the trench 111 as in this modification, ion implantation can be performed after removing the dry etch residues with a buffered hydrofluoric acid solution. This prevents variations in the characteristics of the Schottky barrier diode 1 caused by etch residues that are hardened by ion implantation and cannot be removed.
The second embodiment of the invention differs from the first embodiment mainly in that the Schottky barrier diode does not have a guard ring. Hereinafter, descriptions of the same features as in the first embodiment will be omitted or simplified.
(Configuration of the Schottky Barrier Diode)
In
The Schottky barrier diode 2 includes the n-type semiconductor layer 11 formed of a gallium oxide-based semiconductor and having the trench 111 defining the mesa portions 112 on the upper surface, the high-resistance region 14 that is provided under the trench 111 of the semiconductor layer 11 and contains a p-type impurity, the insulating film 15 that is provided so as to cover at least the bottom surface among the inner surfaces of the trench 111, the anode electrode 16 that is provided on the semiconductor layer 11 through the insulating film 15 and connected to the mesa portions 112, and the cathode electrode 17 provided directly or through another layer on the lower surface of the semiconductor layer 11, in the same manner as the Schottky barrier diode 1 in the first embodiment.
The Schottky barrier diode 2 does not include the guard ring 18 and the annular protrusion 113 surrounding the mesa portions 112. In addition, in the example shown in
(Method for Manufacturing the Schottky Barrier Diode)
An example of a method for manufacturing the Schottky barrier diode 2 will be described below.
Firstly, as shown in
The SiO2 film 51 is formed to a thickness of not less than 100 nm and not more than 2000 nm by sputtering. The photoresist 52 is processed into the pattern of the mesa portions 112 by lithography.
Next, as shown in
A gas used for etching of the SiO2 film 51 is a NF3 gas, a CF4 gas, a C4F8 gas, or a CHF3 gas. A gas used for etching of the semiconductor layer 11 is a Cl2 gas or a BCl3 gas. The depth of the trench 111 is not less than 1 μm and not more than 3 μm.
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
The insulating film 15 is formed to a thickness of not less than 50 nm and not more than 200 nm by CVD. An Al2O3 film may additionally be formed to a thickness of not less than 10 nm and not more than 30 nm on the TEOS film by ALD so that the stacked film composed of the TEOS film and the Al2O3 film is provided as the insulating film 15. In this case, the Al2O3 film acts as an etching stopper film in an etch-back step described next.
Next, as shown in
The resist etch-back is performed by, e.g., fluorine-based dry etching using a fluorine-based etching gas such as CF4 gas, and the etching is finished when the resist on the mesa portions 112 is etched. When the insulating film 15 is a single layer of TEOS film, the insulating film 15 on the mesa portions 112 is also etched at this time. When the insulating film 15 is a stacked film composed of a TEOS film and an Al2O3 film, the Al2O3 film acts as an etching stopper, hence, e.g., the Al2O3 film is etched with an alkaline solution such as TMAH solution and the TEOS film thereunder is etched with a chemical solution containing fluorine, such as hydrofluoric acid. After removing the insulating film 15 on the mesa portions 112, the remaining resist is removed. After that, heat treatment at a temperature of not less than 400° C. and not more than 500° C. is performed as annealing for etching damage recovery.
Next, after cleaning the wafer with a mixture solution of pure water, hydrogen peroxide and sulfuric acid, a stacked film composed of a Mo film, a Ni film and an Au film, etc., is formed to a thickness of not less than 50 nm and not more than 500 nm as the first layer 161 of the anode electrode 16 by vapor deposition, as shown in
Next, as shown in
Subsequently, after protecting the wafer front surface with a resist, the TEOS film formed on the wafer back surface, i.e., the lower surface of the semiconductor substrate 10, is removed using, e.g., a chemical solution containing fluorine, such as hydrofluoric acid. Then, after removing the resist, a stacked film composed of a Ti film and an Au film is formed as the cathode electrode 17 on the lower surface of the semiconductor substrate 10. A Ni film or a Mo film may be provided as a barrier metal between the Ti film and the Au film. When a stacked film composed of a TEOS film and an Al2O3 film is used as the insulating film 15, the insulating film removal step before forming the cathode electrode 17 can be omitted since the insulating film formed on the wafer back surface has already been removed by wet etching in the resist etch-back step described above.
In this modification, firstly, the steps up to the Si ion implantation shown in
Next, as shown in
After that, the resist 54 is removed, and the step of forming the field insulating film 19 and the insulating film 15 shown in
The present inventors found that when a plane orientation of a principal surface of the semiconductor layer 11 is (001) and the length direction of the line-shaped planar pattern of the mesa portions 112 is [010] (the width direction is [100]), nitrogen implanted into the mesa portions 112 in the step shown in
The third embodiment of the invention differs from the second embodiment mainly in that Si, which is an n-type impurity, is not implanted into the semiconductor layer. Hereinafter, descriptions of the same features as in the first and second embodiments will be omitted or simplified.
(Configuration of the Schottky Barrier Diode)
In
The Schottky barrier diode 3 includes the n-type semiconductor layer 11 formed of a gallium oxide-based semiconductor and having the trench 111 defining the mesa portions 112 on the upper surface, the high-resistance region 14 that is provided under the trench 111 of the semiconductor layer 11 and contains a p-type impurity, the insulating film 15 that is provided so as to cover at least the bottom surface among the inner surfaces of the trench 111, the anode electrode 16 that is provided on the semiconductor layer 11 through the insulating film 15 and connected to the mesa portions 112, and the cathode electrode 17 provided directly or through another layer on the lower surface of the semiconductor layer 11, in the same manner as the Schottky barrier diode 1 in the first embodiment.
The Schottky barrier diode 3 does not include the guard ring 18 and the annular protrusion 113 surrounding the mesa portions 112, in the same manner as the Schottky barrier diode 2 in the second embodiment.
In the Schottky barrier diode 3, the plane orientation of the principal surface of the semiconductor layer 11 is (001) and the length direction of the line-shaped planar pattern of the mesa portions 112 is [010] (the width direction is [100]). In this regard, when a plane orientation of a principal surface of the semiconductor substrate 10 is (001), the plane orientation of the principal surface of the semiconductor layer 11 formed thereon by epitaxial growth is also (001).
Surfaces of side portions 112a of the mesa portions 112 contain nitrogen. This nitrogen on the surfaces of the side portions 112a of the mesa portions 112 is the nitrogen that is implanted into the mesa portions 112, diffuse in the [100] direction, which is the width direction of the mesa portion 112, and is concentrated on the surfaces of the side portions 112a. Since the nitrogen concentration in inner portions 112b of the mesa portions 112 is low, electrical resistance of the mesa portions 112 in the vertical direction is low and the implantation of nitrogen into the mesa portions 112 has little effect on the on-resistance of the Schottky barrier diode 2.
In addition, since the nitrogen in the mesa portions 112 has little effect on the on-resistance of the Schottky barrier diode 2, there is no need to cancel out the nitrogen in the mesa portion s112 by Si which is an n-type impurity. Therefore, the mesa portions 112 do not contain an intentionally doped n-type impurity such as Si. That is, the mesa portions 112 do not include the n-type impurity-implanted region 61 into which an n-type impurity such as Si is implanted.
To allow the nitrogen implanted into the mesa portions 112 to effectively accumulate at the surfaces of the side portions 112a and reduce the nitrogen concentration in the inner portions 112b, the pitch width P of the mesa portions 112 arranged in a pattern of lines and spaces is preferably not more than 5 μm.
(Method for Manufacturing the Schottky Barrier Diode)
An example of a method for manufacturing the Schottky barrier diode 3 will be described below.
Firstly, the steps up to the removal of the photoresist 52 and the SiO2 film 51 shown in
Next, as shown in
A dose of nitrogen ion implantation is not less than 5.0×1012 cm−2 and not more than 5.0×1013 cm−2 and implantation energy is not less than 50 keV and not more than 350 keV. In this case, an implantation depth is not less than 0.1 μm and not more than 0.5 μm, and a nitrogen concentration is not less than 5.0×1017 cm−3 and not more than 5.0×1018 cm−3. The annealing is performed at a temperature of not less than 900° C. and not more than 1100° C. in a nitrogen atmosphere or an oxygen atmosphere.
The subsequent Si implantation step can be omitted since the nitrogen concentration in the inner portions 112b of the mesa portions 112 is sufficiently low and the nitrogen does not need to be canceled out by implanting an n-type impurity. Since Si implantation is not performed, the step of implanting nitrogen again to relax the electric field in the terminal end region can be also omitted.
Next, as shown in
The insulating film 15 is formed to a thickness of not less than 50 nm and not more than 200 nm by CVD. An Al2O3 film may additionally be formed to a thickness of not less than 10 nm and not more than 30 nm on the TEOS film by ALD so that the stacked film composed of the TEOS film and the Al2O3 film is provided as the insulating film 15. In this case, the Al2O3 film acts as an etching stopper film in an etch-back step described next.
Next, as shown in
The resist etch-back is performed by, e.g., fluorine-based dry etching using a fluorine-based etching gas such as CF4 gas, and the etching is finished when the resist on the mesa portions 112 is etched. When the insulating film 15 is a single layer of TEOS film, the insulating film 15 on the mesa portions 112 is also etched at this time. When the insulating film 15 is a stacked film composed of a TEOS film and an Al2O3 film, the Al2O3 film acts as an etching stopper, hence, e.g., the Al2O3 film is etched with an alkaline solution such as TMAH solution and the TEOS film thereunder is etched with a chemical solution containing fluorine, such as hydrofluoric acid. After removing the insulating film 15 on the mesa portions 112, the remaining resist is removed. After that, heat treatment at a temperature of not less than 400° C. and not more than 500° C. is performed as annealing for etching damage recovery.
Next, after cleaning the wafer with a mixture solution of pure water, hydrogen peroxide and sulfuric acid, a stacked film composed of a Mo film, a Ni film and an Au film, etc., is formed to a thickness of not less than 50 nm and not more than 500 nm as the first layer 161 of the anode electrode 16 by vapor deposition, as shown in
Next, as shown in
Subsequently, after protecting the wafer front surface with a resist, the TEOS film formed on the wafer back surface, i.e., the lower surface of the semiconductor substrate 10, is removed using, e.g., a chemical solution containing fluorine, such as hydrofluoric acid. Then, after removing the resist, a stacked film composed of a Ti film and an Au film is formed as the cathode electrode 17 on the lower surface of the semiconductor substrate 10. A Ni film or a Mo film may be provided as a barrier metal between the Ti film and the Au film. When a stacked film composed of a TEOS film and an Al2O3 film is used as the insulating film 15, the insulating film removal step before forming the cathode electrode 17 can be omitted since the insulating film formed on the wafer back surface has already been removed by wet etching in the resist etch-back step described above.
The fourth embodiment of the invention differs from the third embodiment in that the Schottky barrier diode has a junction-barrier Schottky (JBS) structure. Hereinafter, descriptions of the same features as in the first to third embodiments will be omitted or simplified.
(Configuration of the Schottky Barrier Diode)
In
The Schottky barrier diode 4 includes the n-type semiconductor layer 11 formed of a gallium oxide-based semiconductor and having the trench 111 defining the mesa portions 112 on the upper surface, the high-resistance region 14 that is provided under the trench 111 of the semiconductor layer 11 and contains a p-type impurity, a p-type semiconductor film 40 that is provided so as to cover at least the bottom surface among the inner surfaces of the trench 111, the anode electrode 16 that is provided on the semiconductor layer 11 through the p-type semiconductor film 40 and connected to the mesa portions 112, and the cathode electrode 17 provided directly or through another layer on the lower surface of the semiconductor layer 11.
The Schottky barrier diode 4 in the fourth embodiment of the invention is a Schottky barrier diode with a JBS structure which includes the p-type semiconductor film 40 formed of NiO, Cu2O or CuO, etc., in place of the insulating film 15 in the Schottky barrier diode 3 in the third embodiment. The Schottky barrier diode 4 may be also a Schottky barrier diode with a JBS structure which includes the p-type semiconductor film 40 in place of the insulating film 15 in the Schottky barrier diode 1 in the first embodiment or the Schottky barrier diode 2 in the second embodiment.
The p-type semiconductor film 40 can be formed by sputtering. The p-type semiconductor film 40 has a similar shape to the insulating film 15 and is removed from the top of the mesa portions 112, etc., by etch-back in the same manner as the insulating film 15. When the p-type semiconductor film 40 is formed of Cu2O or CuO, the p-type semiconductor film 40 can be wet etched using an acidic solution such as buffered hydrofluoric acid solution, diluted aqua regia, or dilute sulfuric acid. When the p-type semiconductor film 40 is formed of NiO, the p-type semiconductor film 40 can be dry etched using an etching gas containing chlorine, such as BCl3.
In the Schottky barrier diode 4, a p-n diode formed by the p-type semiconductor film 40 and the n-type semiconductor layer 11 is formed on the bottom surface of the trench 111 outside the mesa portions 112, which provides high surge current resistance.
(Effects of the Embodiments)
In the first to fourth embodiments, by providing the high-resistance region under the trench of the semiconductor layer, it is possible to provide a Schottky barrier diode with a trench MOS structure that has an even higher withstand voltage than the known art.
In the first to thins embodiments, the high-resistance region 14 may be formed using Mg instead of nitrogen. The conditions for Mg ion implantation are similar to the conditions for nitrogen ion implantation, and are a dose of not less than 5.0×1012 cm−2 and not more than 5.0×1013 cm−2 and implantation energy of not less than 100 keV and not more than 500 keV. In this case, a depth of the high-resistance region 14 is not less than 0.1 μm and not more than 0.5 μm, and a concentration is not less than 5.0×1017 cm−3 and not more than 5.0×1018 cm−3. To effectively exert the electric field relaxation effect of the high-resistance region 14, it is preferable to satisfy a relationship W×Nd<D×Na, where W is a width of a depletion layer formed in the semiconductor layer 11 from the bottom surface of the trench 111 in the depth direction when a reverse voltage is applied, Nd is a donor concentration in the high-resistance region 14, D is a depth of the high-resistance region 14 from the bottom surface of the trench 111, and Na is an acceptor concentration in the high-resistance region 14. However, nitrogen diffuses less by annealing after implantation than Mg and allows the high-resistance region 14 to maintain high resistance more easily. In addition, when the plane orientation of the principal surface of the semiconductor layer 11 is (001) and the length direction of the line-shaped planar pattern of the mesa portions 112 is [010] (the width direction is [100]), nitrogen implanted into the mesa portions 112 effectively diffuses to the surfaces of the side portions and this results in a significant decrease in the nitrogen concentration inside the mesa portions 112 as described above, but the same effect is not obtained when Mg is used instead of nitrogen.
In addition, an HfO2 film, a ZrO2 film, a Y2O3 film, a Si3N4 film, or a stacked film composed of not less than two of these films may be used in place of the Al2O3 film used for the insulating film 15 in the first to third embodiments.
In addition, although a gallium oxide-based semiconductor is used as the material for the semiconductor substrate 10 and the semiconductor layer 11 of the Schottky barrier diodes 1 to 4 in the first to fourth embodiments, a wide-bandgap semiconductor other than the gallium oxide-based semiconductor, such as SiC, may also be used. The wide-bandgap semiconductor here means a semiconductor having a bandgap of not less than 3.0 eV. In addition, the n-type impurity and the p-type impurity used in the semiconductor substrate 10 and the semiconductor layer 11 are appropriately selected and used according to the material of the semiconductor layer 11. In addition, the conductivity types (n-type and p-type) of the doped impurities and the members of the Schottky barrier diodes 1 to 4 may be reversed.
That is, according to an aspect of the invention, it is possible to provide the following Schottky barrier diodes.
Although the embodiments of the invention have been described, the invention is not intended to be limited to the embodiments, and the various kinds of modifications can be implemented without departing from the gist of the invention. In addition, the constituent elements in the embodiments can be arbitrarily combined without departing from the gist of the invention. In addition, the invention according to claims is not to be limited to the embodiments described above. Further, it should be noted that not all combinations of the features described in the embodiments are necessary to solve the problem of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-153043 | Sep 2022 | JP | national |
