The invention relates to LDMOS (laterally diffused metal oxide semiconductor) devices. The invention is applicable to LDMOS which is used as a power switch (able to switch amperes of current). The requirements of a POWER MOSFET (like the LDMOS) are to minimize switching losses. In particular it relates to LDMOS devices implemented in a (Bipolar CMOS DMOS) BCD process.
LDMOS (laterally diffused metal oxide semiconductor) transistors are commonly used in RF/microwave power amplifiers, e.g., in base-stations where the requirement is for high output power with a corresponding drain to source breakdown voltage usually above 60 volts. These transistors are fabricated by growing an epitaxial silicon layer on a more highly doped silicon substrate.
A typical LDMOS is shown in
One of the drawbacks of an LDMOS device is the conduction loss in the inherent body diode of the device. Also, due to minority carrier accumulation the reverse recovery time is slow. Hence the LDMOS suffers from high dynamic losses due to the slow reverse recovery times.
One prior art solution is to include an external Schottky diode. However due to the high inductance of the package and printed circuit board the benefits are diminished. This is illustrated in the circuit diagram of
According to the invention, there is provided an LDMOS device comprising a MOSFET and a Schottky diode integrated into the device adjacent the MOSFET. The MOSFET may include a lightly doped n-type region, typically in the form of an n-epitaxial region in which the n+ source is formed, and the Schottky diode may be formed by providing a metal or metalized region that forms a diode with the lightly doped n-type region. The metalized region may be a silicide region e.g., cobalt silicide. The silicide may be arranged to abut a lightly doped intermediate region that abuts the lightly doped n-type region. The MOSFET may be a butted source body device with a p-body and the n+ source formed in the same active region. The lightly doped n-type region may be an n-epitaxial region and the lightly doped intermediate region may be defined by the p-body, which may be contacted by means of at least one p+ body contact region. The source may be divided into multiple n+ source regions by intermediate p-body regions. In order to provide a junction between the silicide and the n-epitaxial region the n+ source regions may be blocked in the region defining the Shottky diodes. The MOSFET may include an n+ source and an n+ drain formed in the n-epitaxial region, the n-epitaxial region being formed on a p-type region, e.g. a p-substrate or p-epitaxial region grown on a substrate. The p+ body contact region, p−-body, and n+ source may be electrically tied together, e.g., by means of a common metal layer. The n+ source may include multiple n+ source regions separated by p-body regions to increase the safe operating area of the LDMOS. Each Schottky diode may be surrounded by a p+ ring for edge termination to reduce leakage. The p+ ring may be defined by the p+ contact region to the p-body.
Further, according to the invention, there is provided a method of reducing forward conduction loss in an LDMOS device, comprising integrating a Schottky diode with the LDMOS device. The LDMOS device may include a lightly doped n-type region and the Schottky diode may be formed by forming a metal or metalized region adjacent the lightly doped n-type region. The lightly doped n-type region may comprise an n-epitaxial region, which may be formed on a p-region e.g., a p-well region or p-body. The LDMOS device may include an n+ source and an n+ drain. The n+ source may include multiple n+ source regions, which may be separated by p-type regions, e.g., regions of a p-body. The metal or metalized region may comprise a silicided region, e.g., a cobalt silicide. In order to allow the silicided region to be formed adjacent the n-epitaxial region the formation of one or more of the n+ source regions may be blocked. The number of blocked n+ source regions can be increased to further reduce forward conduction loss. Typically the n+ source regions of an LDMOS are formed in a p-body, thus the silicide may be spaced from the n-epitaxial region by the p-body. The silicide region may be formed over the p-body.
Still further according to the invention, there is provided a method of reducing reverse recovery time in an LDMOS device, comprising integrating a Schottky diode with the LDMOS device. The LDMOS device may include a lightly doped n-type region and the Schottky diode may be formed by forming a metal or metalized region adjacent the lightly doped n-type region. The lightly doped n-type region may comprise an n-epitaxial region formed on a p-bulk. The LDMOS device may include an n+ source and an n+ drain. The n+ source may include multiple n+ source regions, which may be separated by regions of the p-body. The metal or metalized region may comprise a silicided region, e.g., a cobalt silicide. In order to allow the silicided region to be formed adjacent the n-epitaxial region the formation of one or more of the n+ source regions may be blocked. Typically the n+ source regions of an LDMOS are formed in a p-body, thus the silicide may be spaced from the n-epitaxial region by the p-body. The silicide region may be formed over the p-body.
The present invention provides an LDMOS device with integrated Schottky diode.
Schottky diodes are formed when a metal plate is brought into contact with lightly doped n-type silicon. As depicted in
The Schottky diode also reduces the reverse recovery loss. Since the Schottky diode is a majority carrier device at low level injection, the minority carrier storage time is eliminated, thereby providing for a faster reverse recover time Trr. Trr is depicted by reference numeral 520 on curve 530.
Consider again the external Schottky diode circuit of
The present invention therefore provides substantial loss reduction, both regarding forward conduction losses as well as reverse recovery losses. One implementation of the LDMOS with integrated Schottky is shown in
In order to integrate the Schottky diode without adding process steps and thus additional cost, the present invention implements the Schottky diode using the same process steps as those used for the LDMOS. In an LDMOS formed using a BCD process, the Schottky is also implemented in the BCD process flow.
By eliminating the highly doped n+ source from the region 804 a lightly doped region is provided in the form of an underlying epitaxial layer. This is best shown in
The cobalt silicide forming the anode of the Schottky diodes will, if a typical LDMOS process is used, be formed on top of the p-body but will nevertheless provide a Schottky diode with the underlying lightly doped n-epitaxial region.
The present invention thus provides an elegant way of reducing forward conduction loss and reverse recovery time in an LDMOS while maintaining the same process steps. Therefore if a Bipolar CMOS DMOS (BCD) process is used in forming the LDMOS, the present invention allows the BCD process to be used in forming an integrated Schottky diode, in accordance with the invention.
In the above embodiments the Schottky diodes were formed in the source/body active region. Schottkys are leakier than regular diodes, hence, only a selected few n+ regions were removed in the source/body active region. The number of n+ source regions eliminated to support Schottky diodes depends on the degree to which high power current has to be supported by the device and the amount of leakage that is acceptable. It will also be noted that each Schottky diode region is surrounded by a p+ ring for edge termination, to reduce leakage. In the above embodiments this is achieved by shorting out the p+ body contact region 126, p-body 124 and n+ source regions 122 by means of a layer of cobalt salicide.
While the implementation was described with respect to particular embodiments, it will be appreciated that the integrated Schottky can be implemented in different ways to achieve integrated Schottky diodes in the source/body active region. Also as discussed above, the number of Schottky diodes created will vary depending on the application.