Patent Application
20060076639
A Schottky diode is formed at the junction of a metal and a semiconductor material that is characterized by a surface charge in the metal and an equal but opposite space charge in the semiconductor at thermal equilibrium. The charge distribution of a Schottky diode is similar to that of a p-n junction diode with a corresponding similar field distribution. The primary electric current in a Schottky diode, however, is majority carrier current, whereas the primary electric current in a p-n junction diode is minority carrier current. The dominant transport mechanism in a Schottky diode is thermionic emission of majority carriers from the semiconductor material to the metal. A Schottky diode is characterized by a rectifying current-voltage relationship with a high-resistance reverse bias direction and a relatively low-resistance forward bias direction.
For high-speed applications, it is desirable for a Schottky diode to have a fast switch-off time, a low series resistance, a low capacitance, and a low reverse-bias leakage current.
The switch-off time of a Schottky diode is increased by reducing the series resistance and reducing the capacitance. The series resistance of a Schottky diode typically is determined by the doping level in the semiconductor material. The Schottky diode capacitance typically is reduced by minimizing the size of the junction area between the metal and the semiconductor material and by placing the Schottky diode far away from large metallic structures, such as bonding pads and the like.
A variety of different approaches for reducing the reverse bias leakage currents in a Schottky diode have been proposed. In one approach, a contact opening through an insulating layer and a thermal oxide layer is overetched to form a shallow trench in an underlying silicon substrate. A metal layer is deposited within the shallow trench and sintered to form a silicide layer contacting the silicon substrate at the bottom and sidewalls of the shallow trench. A barrier layer is formed over the silicide layer and a second metal layer is deposited over the barrier layer to complete the Schottky diode.
In one aspect of the invention, a Schottky diode includes a semiconductor material, and a metal material forming a Schottky barrier junction with the semiconductor material, wherein a cavity having a lateral dimension of at least 200 nm (nanometers) is adjacent to the Schottky barrier junction.
In another aspect, the invention features a method of forming a Schottky diode. In accordance with this inventive method, a semiconductor surface is provided. A dielectric structure defining an opening to the semiconductor surface is formed. A contact structure extending through the opening in the dielectric structure is formed to form a Schottky barrier junction with the semiconductor surface, wherein at the semiconductor surface at least a portion of the Schottky barrier junction is spaced apart from the dielectric structure by a lateral distance of at least 200 nm.
In another aspect of the invention, a Schottky diode includes a semiconductor surface, a dielectric structure, and a contact structure. The dielectric structure defines an opening to the semiconductor surface. The contact structure extends through the opening in the dielectric structure to form a Schottky barrier junction with the semiconductor surface. The contact structure comprises a bonding pad structure that overlies the Schottky barrier junction and at least a portion of the dielectric structure and is electrically connected to the Schottky barrier junction.
Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.
In the following description, like reference numbers are used to identify like elements. Furthermore, the drawings are intended to illustrate major features of exemplary embodiments in a diagrammatic manner. The drawings are not intended to depict every feature of actual embodiments nor relative dimensions of the depicted elements, and are not drawn to scale.
Referring to
The Schottky diode embodiments described in detail below incorporate Schottky barrier junctions with respective portions that are laterally spaced apart from dielectric material at the semiconductor surface where the junction is formed by a distance of at least 200 nm. As used herein, the terms “lateral” and “laterally” relate to directions and dimensions that are substantially parallel to the semiconductor surface where the Schottky barrier junction is formed. The spacing between the Schottky barrier junctions and the dielectric material has been observed to unexpectedly improve the performance of these embodiments by reducing the reverse bias leakage currents exhibited by the Schottky barrier junctions. In addition, these embodiments also incorporate novel dielectric structures, which enable bonding pads to be disposed over the Schottky barrier junctions. In this way, the dielectric structures obviate the placement of the bonding pads far away from the Schottky barrier junctions and thereby allow a significant reduction in the amount of die area needed to implement a the Schottky diode.
The semiconductor material 12 may be any type of semiconductor material, including any type of elemental semiconductor material (e.g., silicon or germanium) or compound semiconductor material (e.g., a III-V semiconductor material, such as gallium arsenide and indium phosphide, or a II-VI semiconductor material, such as zinc selenide and cadmium sulphide). The semiconductor material may be an epitaxial semiconductor film or it may be a bulk semiconductor material. The semiconductor material 12 may be doped n-type or p-type. In general, the doping level should be below the level at which the junction 20 becomes ohmic. An exemplary doping level range for the semiconductor material 12 is 1015-1017 atoms per cubic centimeter (cm3).
The metal material 14 forms a Schottky barrier junction 20 with the semiconductor material 12. The metal material 14 may by any type of metal or metal alloy that forms a Schottky barrier junction 20 with the semiconductor material 12. The metal or metal alloy is referred to herein as a Schottky metal. Exemplary Schottky metals include metals and alloys formed from one or more of the following: platinum, hafnium, cobalt, tantalum, palladium, and titanium.
At least a portion of the Schottky barrier junction 20 is spaced apart from dielectric material 21 at the semiconductor surface where junction 20 is formed by a lateral distance of at least 200 nm. In particular, one or more cavities 22, 24, which have lateral dimensions of at least 200 nm, are juxtaposed with the Schottky barrier junction 20. The cavities 22, 24 may be part of a single cavity-defining structure or they may be discrete cavities separated from one another by regions of material. Each cavity constitutes an unfilled space within a mass of material that encloses the cavity. The enclosing mass of material may have a uniform composition or a nonuniform composition. In the illustrated embodiment, the cavities 22, 24 are disposed at the periphery of the Schottky barrier junction. In some implementations, the cavities 22, 24 are part of a single cavity structure that surrounds the Schottky barrier junction 20. In one of these implementations, the surrounding cavity structure forms an annular ring around the Schottky barrier junction 20. In some implementations, the metal material 14 that forms the Schottky barrier junction 20 also forms at least one wall of each cavity such that the Schottky barrier junction extends right up to the cavities 22, 24. In other implementations, one or more of the cavities 22, 24 are spaced apart from the Schottky barrier junction 20 by a lateral distance within a range of about 0.1 nm to about 100 nm. In some implementations, at least some of the non-cavity space between the metal material 14 and the dielectric material 21 is filled with a non-dielectric, non-Schottky-barrier-forming material, such as a non-Schottky metal or metal alloy.
In the illustrated embodiment, the first electrode 16 is connected to a lo voltage source 26 and the second electrode 18 is connected to a ground potential 28. In other embodiments, the first and second electrodes 16, 18 may be connected to different voltage levels. The voltage level (V) applied across the Schottky diode 10 determines the current level that flows through the device.
Under typical operating conditions, the Schottky diode 10 exhibits a rectifying current-voltage relationship: under forward bias, a forward current flows through the Schottky diode 10; and under reverse bias, only a small reverse bias leakage current flows through the device. When the semiconductor material 12 is doped n-type, a positive voltage (V>0) drives the Schottky diode 10 into forward bias and a negative voltage (V<0) drives the Schottky diode 10 into reverse bias. In contrast, when the semiconductor material 12 is doped p-type, a negative voltage (V<0) drives the Schottky diode 10 into forward bias and a positive voltage (V>0) drives the Schottky diode 10 into reverse bias.
In the illustrated embodiment, the first and second electrodes 16, 18 are positioned to generate electric fields that drive electric currents through the semiconductor material roughly orthogonally with respect to the Schottky barrier junction 20. In other embodiments, the first and second electrodes 16, 18 may be located at other positions. For example, in one embodiment, the first and second electrodes 16, 18 are located on the same side of the Schottky barrier junction and generate electric fields that drive electric currents through the semiconductor material roughly parallel to the Schottky barrier junction.
The dielectric structure 32 includes a stack of a first dielectric layer 36, a second dielectric layer 38, and a third dielectric layer 40. The first dielectric layer 36 forms sidewalls of the cavities 22, 24. The second dielectric layer 38 forms a projection that overhangs the semiconductor substrate 30 and forms top walls of the cavities 22, 24. The third dielectric layer 40 defines a tapered top portion of an opening that extends through the dielectric stack to the surface of the semiconductor substrate 30. The dielectric layers 36-40 may be formed of any type of dielectric material. In some implementations, the first dielectric layer 36 and the second dielectric layer 38 are formed of materials that are selectively etchable with respect to each other. This feature allows the cavities 22, 24 to be defined by selective removal of a portion of the first dielectric layer 36 under the second dielectric layer 38. In the illustrated embodiment, the third dielectric layer 40 is formed of a material that can be etched anisotropically to form the tapered top portion of the opening in the dielectric structure 32.
The contact structure 34 includes a Schottky metal layer 42 and an overlying top metallization 44. The Schottky metal layer 42 forms the Schottky barrier junction 20 with the semiconductor substrate 30. The overlying top metallization 44 is electrically connected to the Schottky metal layer 42 and is disposed over the Schottky barrier junction 20 and at least a portion of the dielectric structure 32. The top metallization 44 includes a bonding pad structure 46 that is configured to be wirebonded to, for example, an external electronic component. In some implementations, the top metallization 44 intrudes into and at least partially fills the space between the Schottky metal layer 42 and the sidewalls of the first dielectric layer 36. In these implementations, the reduced leakage current effects of the spacing between the Schottky metal layer 42 and the dielectric layer 36 are still observed.
As shown in
In one exemplary implementation, the substrate 30 is formed of a bulk silicon chip with an overlying epitaxial silicon film. The first dielectric layer 36 is formed of a 120 nm silicon oxide layer, the second dielectric layer 38 is formed of an 180 nm silicon nitride layer, and the third dielectric layer 40 is formed of a 1.5 micrometer (μm) silica film, such as a film formed by a tetraethylorthosilicate (TEOS) deposition. The Schottky metal layer 42 is formed of a 100 nm titanium film and the top metallization includes a bottom layer formed of a 150 nm tungsten/nickel alloy film and a top layer formed of a 700 nm gold film. In this implementation, the lateral dimensions are as follows: D1 is 8 μm; D2 is 9 μm; D3 is 50 μm; and D4 is 200 μm.
In accordance with this method, the dielectric structure 32 is formed (block 50). This process involves growing or depositing the first, second and third dielectric layers 36, 38, 40.
After the dielectric structure 32 has been formed (block 50), an opening is etched through the dielectric structure 32 to the first dielectric layer 36 (block 52). In this process, contact mask initially is deposited on the third dielectric layer 40 to define the contact opening. With respect to the exemplary implementation described above in which the dielectric structure is formed of a stack of a TEOS dielectric, silicon nitride, and silicon oxide, the opening is etched through the TEOS dielectric layer 40 using an isotropic dry oxide etching process, such as reactive ion etching, and a dry nitride etching process is used to etch through the silicon nitride layer 38.
Next, the first dielectric layer 36 is selectively etched to expose the semiconductor substrate 30 and to define the cavity structure 22, 24 (block 54). The selective etch preferentially etches the underlying dielectric layer 38 relative to the overlying dielectric layer 38. In this way, the selective etching process removes a portion of the first dielectric layer 36 under the second dielectric layer 38, which projects over the resulting cavity areas. With respect to the exemplary implementation described above in which the dielectric structure is formed of a stack of a TEOS dielectric, silicon nitride, and silicon oxide, the first silicon oxide layer 36 is etched using a wet oxide etching process. During this process, the selective etching process may concurrently anisotropically etch the third dielectric layer 40 to form the tapered sidewalls at the top portion of the opening.
The Schottky metal contact 42 is formed by a front metal deposition process that involves depositing a Schottky metal layer through the opening onto the exposed surface of the semiconductor substrate 30 (block 56). A contact metal mask is deposited on the Schottky metal layer and the Schottky metal contact region is defined lithographically. Non-contact regions of the Schottky metal layer are removed using a contact metal etching process. The residual contact metal mask also is removed.
The top metallization 44 is formed by depositing the top metallization layer (or layers) into the opening over the Schottky metal layer 42 and over at least a portion of the dielectric structure 32 (block 58). A pad metal mask is deposited on the top metallization and the pad metal contact region is defined lithographically. Non-contact regions of the top metallization are removed using a pad metal etching process. The residual pad metal mask also is removed.
The semiconductor substrate 30 may be thinned and a backside metallization may be deposited on the side of the semiconductor substrate 30 to complete the Schottky diode 10 (block 60).
Other embodiments are within the scope of the claims.
For example,
