(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of designing a seal ring.
(2) Description of the Prior Art
The creation of semiconductor devices comprises numerous complex and mutually cooperative steps of semiconductor processing during which a large variety of materials and techniques are used. Processing of semiconductor devices is performed in a serial processing stream, which implies that each of the steps of the sequential processing must be essentially error free so as to avoid accumulative errors and the severe negative yield impact that would result therefrom.
This latter requirement implies that semiconductor materials are created where they are required to be created, strictly controlling the occurrence of such materials in any other than the required design configuration. For instance, the accumulation of undesired matter in a location may result in unwanted or catastrophic interconnects or shorts or may create unacceptable parasitic components that have a serious negative effect on the performance and reliability of the created devices.
Since device feature size is continuously being decreased, the control of alien matter must be accordingly increased. This requires that all possible measures must be taken to prevent any negative impact of unwanted environmental particles that are typically present in a semiconductor manufacturing facility.
As a source of particle contamination can be identified the work environment, which comprises particles that originate from a source other than the wafer that is being processed. These particles are typically controlled by extensive steps of clean room creation and maintenance and depend in this context on filtering and a strict control of the working environment, mostly achieved by filtering the components of this working environment.
As another source of particle contamination can be identified the wafer that is being processed since, during processing the wafer is either directly affected by for instance moving the wafer to a different location or is affected by a processing step to which the wafer is subjected at any given time.
This latter source of particle contamination takes on a more serious form if it is considered that wafer processing is becoming more complex, with increasingly more steps of processing sequentially being performed on a wafer before the processing cycle is completed.
This aspect of contamination is further aggravated by the increasingly complex and diverse nature of the materials that are applied to a wafer such as interconnect metals and dielectrics that are applied over a wide range of temperatures.
For this and other reasons, it has become accepted practice to provide a seal ring whereby as a good example of such an application can be cited U.S. Pat. No. 5,723,385 (Shen et al.), which provides a wafer edge seal ring for reduced particle and contaminant generation during wafer processing. This latter application provides for depositing layers at the perimeter of a wafer and gradually spacing the overlying layers at an increased distance from the edge of the wafer.
U.S. Pat. No. 5,891,808 (Chang et al.) teaches a seal ring process and an etch stop.
U.S. Pat. No. 5,723,385 (Shen et al.) shows a seal ring process.
U.S. Pat. No. 6,362,524 B1 (Blish et al.) reveals an edge seal ring for a copper damascene process.
U.S. Pat. No. 6,300,223 B1 (Change et al.) shows a seal ring process.
A principle objective of the invention is to create a seal ring around the perimeter of a substrate such that problems of etch stop layer damage is prevented while simultaneously creating dissimilar features such as seal ring vias having dissimilar Critical Dimensions of the seal ring.
In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such as seal ring vias, such that the difference in etch sensitivity between the created seal ring and the other device features such as via holes is removed. All etching of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.
a through 1c show cross sections of conventional hole etching.
Prior Art has addressed concerns of punch through of an etch stop layer by selecting the Critical Diameter (CD) of a seal via as being smaller than the CD of a seal ring. This requires selecting the surface area that is being etched such that the etch of the seal ring and the seal via holes completes at about the same time. The invention does not follow this approach. The invention is not based on selecting the surface area of the areas that are concurrently being etched but selects the width of the seal ring and the diameter of the seal vias as the controlling parameters that enable the concurrent completion of the seal ring and the seal vias.
The invention addresses the creation of a seal ring, whereby the seal ring comprises a trench and therewith associated seal ring vias. These two features of trench and vias are simultaneously etched, a process that may result in damage to the applied etch stop layer in view of and caused by the different Critical Dimensions of these two elements. The invention addresses this concern of etch layer damage or punch through and provides a method whereby this damage is avoided.
Referring specifically to the cross section of
Highlighted in the cross sections of
In comparing diameter 11 with diameter 13, it can be observed and is intended that the value of 11 is larger than the value of 13, meaning that the 15 opening is wider than opening 17.
If both openings 15 and 17 are created using identical methods and conditions of surface etch, opening 15 will be created at a faster rate than opening 17. If therefore the etch for both openings 15 and 17 is performed such that the etch time is also identical, then the etch of opening 15 will affect the surface of etch stop layer 12 before the etch of opening 17 is completed. The result of this is shown in the cross section of
The cross sections of
If, as is shown in the cross section of
It is clear that, for a processing environment in which features of different cross sections are simultaneously created as part of one processing cycle, measures are required to prevent etch stop layer punch through. The invention provides such a method.
The previously highlighted seal ring that is conventionally provided for protective purposes is created in a processing sequence during which additionally via openings are created, as highlighted in the cross section of
A number of the highlighted elements of
It is clear and in line with the previously highlighted cross sections of
Typically, the seal ring 20 is expected to have a higher etch rate that the via opening 22, resulting in the layer 12 being exposed in the surface of layer 12 underlying the seal ring prior to completion of the etch for opening 22. The etch stop layer 12 will therefore typically be punched through over the bottom surface of seal ring 20. The surface of underlying copper layer 16,
The occurrence of etch rate dependency on the diameter of the etched surface is highlighted in
The invention addresses this problem by minimizing the etch rate of the smaller width surface, that is the seal ring 20,
As typical and desired examples of the dimensions that are required to achieve the desired effect of simultaneous completion of the seal ring etch and the via hole etch can be cited a CD(hole) of parameter 23,
By therefore selecting the width 21 of the seal ring 20, shown in the cross section of
The exposed surface of seal ring 26 must therefore be reduced relative to the exposed surface of vias 27, leading to the above formalized relationship between these two entities.
The invention can be further extended by including the creation of alignment marks, whereby the alignment marks take the position of the previously discussed vias as being features having an exposed surface that is smaller than the surface area of a seal ring and that therefore tends to be etched at a slower rate than the seal ring. The surface area of the seal ring must therefore also be adjusted and be reduced with respect to the surface area of the alignment mark.
The invention, which provides a method for the creation of a seal ring over a semiconductor device, can be summarized as follows:
Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.