Number | Name | Date | Kind |
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4532613 | Takemae et al. | Jul 1985 | |
5422857 | Ninomiya et al. | Jun 1995 |
Number | Date | Country |
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0 169 460 A3 | Jan 1986 | EPX |
0 520 788 A3 | Dec 1992 | EPX |
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Toshihiko Hirose, et al., "A 20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding Architecture", pp. 1068-1074, IEEE Journal of Solid-State Circuits, vol. 25, No. 5, Oct. 1990. |