Patent Application
20050145915
The present invention relates in general to semiconductor devices and, more particularly, to a selective epi-region method for integration of vertical power MOSFET and lateral driver devices.
Metal oxide semiconductor field effect transistors (MOSFETs) are commonly used in power transistor applications such as switching power supplies, power conversion, power management, energy systems, telecommunications, personal computer applications, motor control, automotive, and consumer electronics. Power devices generally refer to transistors and other semiconductor devices that can switch about 1.0 ampere or more of conduction current. Power MOSFETs are well known as high input impedance, voltage controlled devices which require only a relatively small charge to initiate turn-on from simple drive circuitry. The Power MOSFET ideally exhibits high drain-to-source current carrying capacity, low drain-to-source resistance (RDSon) to reduce conduction losses, high switching rate with low switching losses, and high safe operating range (SOA) which provides the ability to withstand a combination of high voltage and high current.
While some power devices are discrete, it is common to integrate power devices with drivers. Accordingly, power MOSFETs, which can be either lateral or vertical devices, can be used in combination with a lateral driver circuit. The driver circuit may be as simple as a p-channel transistor and an n-channel transistor connected in a totem-pole arrangement. Other driver circuits are known to have more features. The junction between the drain of the p-channel transistor and the drain of the n-channel transistor is the output of the driver circuit, which is coupled to the gate of the power MOSFET. In one operating mode, the p-channel transistor of the driver circuit is turned on to source current directly into the gate of the power MOSFET. In another operating mode, the n-channel transistor of the driver circuit is turned on to sink current directly away from the gate of the power MOSFET. The driver circuit must supply sufficient current to charge and discharge the gate voltage of the power MOSFET. The driver circuit thus operates to turn on and off the power MOSFET in a rapid and efficient manner.
The driver circuit is typically a low voltage device, operating in the range of 5-25 volts. The power MOSFET is a higher voltage device, operating in the range of 20-30 volts. The lateral driver circuit is usually placed on the same base silicon substrate as the power device. For efficient layout considerations, the lateral driver circuit is often located in proximity to the power MOSFET.
In constructing the lateral devices, an N-epi layer is disposed above the silicon substrate. A first p-well is formed in the N-epi layer for the n-channel transistor, and an n-well is formed within the first p-well for the p-channel transistor. A second p-well is formed in the N-epi layer, in proximity to but separated from the first p-well by N-epi, for the power device. The N-epi layer under the power MOSFET is made a certain thickness, with low resistivity, to provide isolation from the high voltage components. The thickness of the N-epi layer needed to provide the necessary breakdown voltage for the power MOSFET is less than the thickness of the N-epi required for the isolation of the lateral driver devices.
Given that the lateral devices and vertical power device are located in proximity to one another and share the same N-epi layer, the N-epi under the power device has non-optimal dimensions. That is, in order to accommodate the isolation requirement for the lateral driver device and given that vertical power device has the same N-epi thickness as the lateral driver device, the N-epi under the power device ends up being thicker than is necessary to achieve the required breakdown voltage protection. The thicker N-epi under the power device increases the RDSon in the conduction state of the power MOSFET, which is undesirable. The isolation requirements of the lateral driver devices has caused the RDSon of the vertical power MOSFET to be less than optimized.
In one embodiment, the present invention is a method of forming a semiconductor device comprising the steps of providing a substrate, removing a portion of the substrate to provide a layer offset in the substrate, forming an epi region of uniform thickness over the substrate, wherein the epi region has a similar offset as the layer offset, and planarizing the epi region so that the epi region over a first portion of the substrate has less thickness than the epi region over a second portion of the substrate.
In another embodiment, the present invention is a method of forming an integrated circuit having a driver device in proximity to a power device comprising the steps of forming a substrate having a driver device area and a power device area, forming a layer offset between the driver device area and the power device area, forming an epi region over the driver device area and the power device area, and planarizing the epi region so that the epi region over the power device area has less thickness than the epi region over the driver device area.
In yet another embodiment, the present invention is a method of forming a first semiconductor device in proximity to a second semiconductor device on an integrated circuit comprising the steps of forming a first layer of semiconductor material with a layer offset between a first semiconductor device area and a second semiconductor device area, forming an epi region over the first semiconductor device area and the second semiconductor device area, and planarizing the epi region such that the epi region over the second semiconductor device area has less thickness than the epi region over the first semiconductor device area.
Referring to
Driver circuit 10 must supply sufficient current to charge and discharge the gate voltage of power MOSFET 12. Power MOSFET 12 is capable of switching more than 1.0 ampere of conduction current I12. Power MOSFET 12 exhibits high drain-to-source current carrying capacity, low drain-to-source resistance (RDSon) to reduce conduction losses, high switching rate with low switching losses, and high safe operating range (SOA) which provides the ability to withstand a combination of high voltage and high current.
Driver circuit 10 includes p-channel transistor 14 and n-channel transistor 16. A control signal is applied to the common gates of transistors 14 and 16. If the control signal is low, then transistor 14 conducts and transistor 16 is turned off. Transistor 14 sources current to the gate of power MOSFET 12 to turn on the power device in a rapid manner. If the control signal is high, then transistor 14 turns off and transistor 16 conducts. Transistor 16 sinks current away from the gate of power MOSFET 12 to turn off the power device in a rapid manner.
Driver circuit 10 operates with a low supply voltage VDD1 on the order of 5-25 volts and ground potential. Power MOSFET 12 operates with a higher supply voltage VDD2 in the range of 20-30 volts or more, and supply voltage VSS2. As noted above, driver circuit 10 and power MOSFET 12 are formed in proximity to one another on the same silicon substrate within IC 20. The lateral devices of driver circuit 10 will require isolation for protection from the higher voltage of power MOSFET 12. At the same time, it is desirable to keep the RDSon of power MOSFET 12 to a low value.
Turning to
In one aspect, N+ layer 24 can be a separate semiconductor layer with respect to substrate 22. In another aspect, N+ layer 24 functions as an extension of, and can be considered an integral part of, substrate 22. In another embodiment, the area defined by substrate 22 and N+ layer 24 can be a single uniform-concentration substrate region. In another view, N+ layer 24 can be omitted altogether.
Mask layer 26 is disposed over a portion of N+ layer 24 corresponding to the vertical power device area, i.e., that area to the right of line A. The portion of N+ layer 24 corresponding to the lateral driver device area, i.e., that area to the left of line A, is unprotected in the subsequent etching process. With mask layer 26 in place, the portion of N+ layer 24 which is under the lateral driver device area is etched away, substantially down to substrate 22. Mask layer 26 is then removed as shown in
The portion of N+ layer 24 that has been etched away constitutes the removed portion of N+ layer 24. The portion of N+ layer 24 that had been under mask layer 26 constitutes the remaining portion of N+ layer 24. The etching process may be stopped before reaching substrate 22, may be stopped at substrate 22, or may continue into substrate 22. The height of offset 28 is thus determined by the original thickness of N+ layer 24, and the degree or amount of etching that takes place, all of which can be controlled by the design and manufacturing process.
An epi region 30 is grown or formed to a relatively uniform thickness of about 6 microns across substrate 22 and N+ layer 24. Epi region 30 receives an N− doping concentration of phosphorus or arsenic on the order of 5*E15 to 5*E16 atoms/cm3. The thickness of epi region 30 above substrate 22 to the left of line A is the same as the thickness of epi region 30 above N+ layer 24 to the right of line A. Accordingly, in the process of forming N-epi region 30, the offset or stair-step 28 between substrate 22 and N+ layer 24 causes a similar offset or stair-step 32 to N-epi region 30, as shown. The offset 32 may be a step function, gradual, angled, or inclined, with a linear or non-linear slope. N-epi region 30 is a single, continuous region.
N-epi region 30 is planarized in
In
It can be seen in
The difference in thickness of the N-epi region under p-well 36 and the N-epi region under p-well 40, which is readily controllable by selecting the desired height of offset 28, allows design considerations for the lateral driver devices and vertical power devices to be independently optimized. Driver circuit 10 has the necessary isolation, while power MOSFET 12 does not suffer from the N-epi overhead as found in the prior art. Power MOSFET 12 has a lower RDSon with the thinner N-epi region under p-well 40.
By creating a vertical or inclined offset or stair-step between substrate 22 and N+ layer 24, forming a uniform thickness of N-epi over both substrate 22 and N+ layer 24, and then planarizing the N-epi region to create an even surface, the desired thicker N-epi region 30 under p-well 36 and the desired thinner N-epi region 30 under p-well 40 are formed to optimize both the design considerations for driver circuit 10 and for power MOSFET 12. N-epi region 30 is grown, as shown in
The present description has given specific dimensions for the different thickness of N-epi region 30. Other dimensions of N-epi region 30, under the lateral driver device area and the vertical power device area, are within the scope of the present invention.
A person skilled in the art will recognize that changes can be made in form and detail, and equivalents may be substituted for elements of the invention without departing from the scope and spirit of the invention. The present description is therefore considered in all respects to be illustrative and not restrictive, the scope of the invention being determined by the following claims and their equivalents as supported by the above disclosure and drawings.
