The present invention relates generally to circuit boards.
Electronic components, such as processors, controllers, and other semiconductor devices, can be mounted on circuit boards that include pathways (also called traces) to interconnect the electronic components. A circuit board, sometimes referred to as a printed circuit board (PCB) or a printed wiring board (PWB), comprises one or more layers of conductive material (e.g., copper) separated and supported by insulating material (e.g., fiberglass-epoxy resin).
To promote adhesion between a conductive layer and an insulating layer in a circuit board, the conductive layer is often roughened to ensure that the adhesion satisfies manufacturing and reliability requirements. A roughened conductive layer, however, results in higher losses during high speed signaling. Hence, there is a conflict between reducing high speed signaling loss, which requires a smoother conductive layer, and ensuring sufficient adhesion between conductive and insulating layers, which requires a rougher conductive layer.
A circuit board and a method for fabricating a circuit board are provided. The circuit board includes a dielectric core comprising a first surface and a second surface and a conductive layer comprising a first surface and a second surface. The first surface of the conductive layer is coupled to the second surface of the dielectric core. A first region of the second surface of the conductive layer is smooth and a second region of the second surface of the conductive layer is rough. The first region of the second surface of the conductive layer is operable to support high speed signaling and the second region of the second surface of the conductive layer is operable to support non-high speed signaling.
The method includes providing a dielectric core comprising a first surface and a second surface, providing a conductive layer comprising a first surface and a second surface, the second surface of the conductive layer being smooth, coupling the first surface of the conductive layer to the secnd surface of the dielectric core, masking a first region of the second surface of the conductive layer, and roughening a second region of the second surface of the conductive layer, wherein the first region of the second surface of the conductive layer remains smooth, the first region of the second surface of the conductive layer being operable to support high speed signaling and the second region of the second surface of the conductive layer being operable to support non-high speed signaling.
The present invention relates generally to circuit boards. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. The present invention is not intended to be limited to the implementations shown, but is to be accorded the widest scope consistent with the principles and features described herein.
Circuit boards are used to mechanically support and electrically interconnect multiple electronic components, such as processors, controllers, and other semiconductor devices. A circuit board, which can be rigid or flexible, includes one or more layers of conductive material separated by insulating material. To interconnect electronic components, pathways (also referred to as traces, lines, or nets) can be formed in a conductive layer through, for instance, chemical etching or laser ablation.
The layers of conductive and insulating material are usually coupled together through, for instance, lamination (i.e., glued together with heat, pressure, and/or vacuum). To ensure that the adhesion between a conductive layer and an insulating layer satisfies manufacturing, assembly, and usage requirements, which are typically measured in terms of peel strength (i.e., the amount of strength required to separate a conductive layer from an insulating layer), a surface of the conductive layer to be coupled to a surface of the insulating layer can be roughened using, for example, a chemical or laser process.
Depicted in
A conductive layer comprising a first surface and a second surface is provided at 204. The second surface of the conductive layer is smooth. In one implementation, the conductive layer is a layer of copper foil. At 206, the first surface of the conductive layer is coupled to the second surface of the dielectric core. A first region of the second surface of the conductive layer is masked at 208 and a second region of the second surface of the conductive layer is roughened at 210. As a result of the masking, the first region of the second surface of the conductive layer remains smooth.
The first region of the second surface of the conductive layer is operable to support high speed signaling and the second region of the second surface of the conductive layer is operable to support non-high speed signaling. In one implementation, high speed signaling is signaling at or above 500 Megahertz (MHz).
By selectively roughening a conductive layer in a circuit board based on location of high speed signal traces, sufficient adhesion can be achieved without compromising electrical performance. Since high speed nets are typically routed in close proximity to one another, isolating high speed signaling region(s) or area(s) should not be too difficult. In addition, with multi-layer circuit boards, not all conductive layers will be signaling layers (e.g., ground layers) and not all signaling layers will include high speed nets. As such, the region(s) or area(s) of conductive material that remain smooth may be small compared to the region(s) or area(s) that are roughened.
Shown in
Illustrated in
Conductive layer 504 is a layer of copper foil in one implementation. A first region 506 of the second surface 504b of conductive layer 504 is smooth and a second region 508 of the second surface 504b of conductive layer 504, which encompasses the area outside of first region 506, is rough. Second region 508 is illustrated as a gray shaded area in
A first region 606 and a third region 610 of the second surface 604b of conductive layer 604, which are operable to support high speed signaling, are smooth while a second region 608 of the second surface 604b of conductive layer 604, which is operable to support non-high speed signaling, is rough. Similar to
Depicted in
At 712, the conductive layer is selectively etched to form a plurality of circuit traces. A surface of a prepreg material is coupled to the second surface of the conductive layer at 714 through, for instance, lamination. The prepreg material may be an uncured fiberglass-epoxy resin and is available in different styles with varying amounts of resin and glass fibers. This allows manufacturers to control thickness between layers and thickness of a circuit board.
Although process 700 is described with reference to a particular ordering of process actions, the ordering may be changed without affecting the scope or operation of the invention. For example, chemical treatment of the second region of the second surface of the conductive layer can occur after etching of the conductive layer in another implementation.
The surface of conductive layer 804 outside of the masked region is roughened in
In
The degree to which the surface of conductive layer 804 is roughened can depend on the type of prepreg material 808 used. Once the required peel strength is achieved, further roughening of the surface will not serve any purpose. In addition, further roughening of the surface will increase manufacturing costs. Hence, the surface of conductive layer 804 should not be roughened any more than it is necessary.
Other steps may have been taken to fabricate circuit board 800, even though those steps are not illustrated in
Shown in
As shown in
In the implementation, only the surface conductive layer 902D has been selectively roughened because, as previously noted, not all conductive layers in a circuit board are signal layers and not all signal layers include traces for high speed signaling. Signal layer 902E, which does not include any high speed nets, and ground layers 902B-902C and 902F-902G have been uniformly roughened. Additionally, a surface of conductive layer 902A facing prepreg material 906A and a surface of conductively layer 902H facing prepreg material 906D have been uniformly roughened since those surfaces will not be used for signaling.
Circuit board 900 also includes power planes 908A and 908B, which have thinner dielectric cores 904A and 904C to maximize capacitance between the planes. Ground planes (not shown) can also have thinner dielectric cores for similar reasons. Thicker conductive layers 902B-902C and 902F-902G may be used to reduce resistance. Power planes 908A and 908B provide a stable reference voltage for signals, distribute power to all devices, and control cross-talk between signals.
While various circuit board implementations and implementations for fabricating a circuit board have been described, the technical scope of the present invention is not limited thereto. It is to be understood by those skilled in the art that various modifications or improvements can be added to the above implementations. It is apparent from the appended claims that such modified or improved implementations fall within the technical scope of the present invention.