Patent Application
20150113349
The present invention relates to testing of a semiconductor device, and more specifically, to automated selective testing of a semiconductor device.
When a semiconductor design such as for a wafer, module, application specific integrated circuit (ASIC), or very large scale integrated circuit (VLSI) is tested, the testing involves a set of commercially available test patterns specific to the product under test. The commercially available test pattern generator output is made platform specific by an on-site test pattern processor that may support several test system platforms, for example. While the test pattern generator provides an efficient source for comprehensive testing of the product, the processing of all the test patterns can become time-consuming. At various stages of development, quick feedback from testing is important to determine, for example, new patterns that must be tested to isolate any issues. Thus the time associated with the test pattern processor processing all the test patterns may present issues.
According to one embodiment of the present invention, a method of testing a semiconductor device includes receiving, at a pattern processor from a test pattern generator, a set of test patterns for testing the semiconductor device; selecting, by a user, a subset of the set of test patterns; cataloging, by the pattern processor, a content of pattern files associated with the subset of the set of test patterns to generate a catalog; and processing, by the pattern processor, the catalog to output test data to the semiconductor device.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
As noted above, the processing of all the test patterns provided by a commercially available test pattern generator can be time consuming and inefficient. Test patterns may be used in many sectors of a product's final test including, for example, power-on, engineering product bring-up, design verification, test coverage, yield analysis, characterization, diagnosis, burn-in, and manufacturing final test. During each of the stages, turn around time (TAT) of the testing plays a major role in determining feasibility, capability, manufacturability, and functionality of a design. In fact, the time and data volume associated with the processing can be one of the most critical items affecting the usefulness of testing designs and test patterns. Embodiments of the system and method described herein facilitate processing of a subset of the test patterns. Embodiments of the invention also facilitate selection of American Standard Code for Information Interchange (ASCII) rather than binary test pattern files.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated
The flow diagrams depicted herein are just examples. There may be many variations to this diagram or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
