Claims
- 1. A stacked gate region of a memory cell comprising:
a field oxide region; a tunnel oxide layer; at least one floating gate layer formed over said tunnel oxide layer; and at least one polysilicon structure formed above and adjacent to said field oxide region, said at least one polysilicon structure is adapted to increase capacitive coupling of said memory cell.
- 2. The stacked gate region of claim 1, wherein said field oxide region is formed in a trench.
- 3. The stacked gate region of claim 1, wherein said at least one polysilicon structure is selected from the group consisting of ear and wing.
- 4. A stacked gate region of a memory cell comprising:
a field oxide region; a tunnel oxide layer; at least one floating gate layer formed over said tunnel oxide layer; and at least one wing formed adjacent to said at least one floating gate layer and over a portion of said field oxide region.
- 5. The stacked gate region of claim 4, wherein said floating gate layer comprises a first deposited and patterned polysilicon layer.
- 6. The stacked gate region of claim 4, wherein said at least one wing comprises a second deposited and patterned polysilicon layer.
- 7. The stacked gate region of claim 4, wherein said at least one wing and said at least one floating gate layer comprise polysilicon.
- 8. The stacked gate region of claim 4, wherein said at least one wing is substantially vertical.
- 9. The stacked gate region of claim 4, wherein said at least one wing is substantially co-planar with said at least one floating gate layer.
- 10. The stacked gate region of claim 4, wherein said at least one wing is adjacent a substantially vertical edge of said at least one floating gate layer.
- 11. The stacked gate region of claim 4, wherein said at least one wing is comprised of a first polysilicon and said at least one floating gate layer is comprised of a second polysilicon, wherein said second polysilicon is different than said first polysilicon.
- 12. A stacked gate region of a memory cell comprising:
a substrate having at least one semiconductor layer; at least one trench formed in said substrate; a tunnel oxide layer formed over at least a portion of said substrate; at least one floating gate layer formed over said oxide layer; field oxide deposited in said at least one trench; and at least one ear formed on said at least one floating gate layer and having only a lower edge thereof in contact with said at least one floating gate layer.
- 13. The stacked gate region of claim 12, wherein said at least one ear has a selected height corresponding to a desired capacitive coupling.
- 14. The stacked gate region of claim 12, wherein said at least one ear is comprised of a first polysilicon and said at least one floating gate layer is comprised of a second polysilicon, wherein said second polysilicon is different than said first polysilicon.
- 15. A stacked gate region of a memory cell comprising:
a substrate having at least one semiconductor layer; a plurality of trenches formed in said substrate; respective field oxide regions formed in said trenches; a tunnel oxide layer formed over said substrate; a floating gate layer formed over said tunnel oxide layer; and a pair of wings located adjacent to opposite ends of said floating gate layer, co-planer with said floating gate layer and over a portion of corresponding ones of said field oxide regions.
- 16. The stacked gate region of claim 15, wherein said floating gate layer comprises a plurality of floating gates and a corresponding pair of wings for each of said plurality of floating gates.
- 17. A stacked gate region of a memory cell comprising:
a substrate having at least one semiconductor layer; a plurality of trenches formed in said substrate; respective field oxide regions formed in said trenches; a tunnel oxide layer formed over said substrate; a floating gate layer formed over said tunnel oxide layer; and a pair of ears formed on opposite ends of said floating gate layer and having only a lower edge thereof in contact with said at least one floating gate layer.
- 18. The stacked gate region of claim 17, wherein said floating gate layer comprises a plurality of floating gates and a corresponding pair of ears for each of said plurality of floating gates.
- 19. A memory cell comprising:
a substrate having at least one semiconductor layer; a source formed in said substrate; a drain formed in said substrate; at least one trench formed in said substrate; a field oxide region formed in said trench; a tunnel oxide layer formed over said substrate; at least one floating gate layer formed over said tunnel oxide layer; at least one polysilicon structure adapted to increase capacitive coupling of said memory cell, and being located above and adjacent to field oxide layer; and a dielectric layer formed over said substrate and said floating gate layer; and a control gate layer formed over said dielectric layer.
- 20. The memory cell of claim 19 wherein said at least one polysilicon structure is selected from the group consisting of at least one ear, and at least one wing.
- 21. A memory cell comprising:
a substrate having at least one semiconductor layer; a source formed in said substrate; a drain formed in said substrate; at least one trench formed in said substrate; a field oxide region formed in said trench; a tunnel oxide layer formed over said substrate; at least one floating gate layer formed over said tunnel oxide layer; at least one wing formed adjacent to said at least one floating gate layer and over a portion of said field oxide region; a dielectric layer formed over said substrate and said floating gate layer; and a control gate layer formed over said dielectric layer.
- 22. The memory cell of claim 21, wherein said at least one wing is comprised of polysilicon.
- 23. The memory cell of claim 21, wherein said at least one wing is substantially vertical.
- 24. The memory cell of claim 21, wherein said at least one wing is substantially co-planar with said at least one floating gate.
- 25. The memory cell of claim 21, wherein said at least one wing is adjacent a substantially vertical edge of said at least one floating gate.
- 26. The memory cell of claim 21 wherein said field oxide is coplanar with a surface of said tunnel oxide layer.
- 27. A memory cell comprising:
a source formed in a substrate; a drain formed in the substrate; a trench formed in the substrate; a field oxide region formed in said trench; a tunnel oxide layer formed over said substrate; at least one floating gate layer formed over said tunnel oxide layer; a pair of polysilicon ears formed on opposite ends of said at least one floating gate layer and having only a lower edge thereof in contact with said at least one floating gate layer; a dielectric layer formed over said substrate and said floating gate layer; and a control gate layer formed over said dielectric layer.
- 28. The memory cell of claim 27, wherein said at least one ear is comprised of polysilicon.
- 29. The memory cell of claim 27, wherein said at least one ear is substantially vertical.
- 30. The memory cell of claim 27, wherein said at least one ear is above and adjacent to a substantially vertical edge of said field oxide.
- 31. The memory cell of claim 27 wherein said field oxide is coplanar with a surface of said at least one floating gate.
- 32. A memory device comprising:
a plurality of memory cells aligned in a plurality of rows and columns, each memory cell including:
a source formed in a common region with a source of an adjacent memory cell, a drain formed in another common region with a drain of an adjacent memory cell,
a floating gate, a field oxide region to electrically isolating adjacent said memory cells, at least one polysilicon structure formed over the substrate above and adjacent to said field oxide region, a dielectric layer formed over said floating gate layer,
a control gate layer formed over said dielectric layer, said control gate is associated with a row of said plurality of memory cells, formed integral to a common word line associated with said row; a conductive bit line connected to said drain of each memory cell in a column of said plurality of memory cells; and a common source line connected to said source of each memory cell.
- 33. The memory device of claim 32 wherein said at least one polysilicon structure is at least one ear located on said floating gate.
- 34. The memory device of claim 32 wherein said at least one polysilicon structure is at least one wing located adjacent and co-planar to said floating gate.
- 35. A memory device comprising:
a plurality of memory cells aligned in a plurality of rows and columns, each memory cell including:
a source formed in a common region with a source of an adjacent memory cell, a drain formed in another common region with a drain of an adjacent memory cell, a floating gate, a field oxide region to electrically isolating adjacent said memory cells, a pair of wings formed adjacent to said floating gate and over a portion of said field oxide region, a dielectric layer formed over said floating gate layer, a control gate layer formed over said dielectric layer, said control gate is associated with a row of said plurality of memory cells, formed integral to a common word line associated with said row; a conductive bit line connected to said drain of each memory cell in a column of said plurality of memory cells; and a common source line connected to said source of each memory cell.
- 36. A memory device comprising:
a plurality of memory cells aligned in a plurality of rows and columns, each memory cell including:
a source formed in a common region with a source of an adjacent memory cell, a drain formed in another common region with a drain of an adjacent memory cell, a floating gate, a field oxide region to electrically isolating adjacent said memory cells, a pair of ears formed over the floating gate layer at opposite ends thereof in proximity of, but not in contact with the field oxide region, a dielectric layer formed over said floating gate layer, a control gate layer formed over said dielectric layer, said control gate is associated with a row of said plurality of memory cells, formed integral to a common word line associated with said row; a conductive bit line connected to said drain of each memory cell in a column of said plurality of memory cells; and a common source line connected to said source of each memory cell.
- 37. A computer system comprising:
at least one processor; a system bus; and a memory device coupled to said system bus, said memory device including one or more memory cells, each memory cell including at least one stacked gate region comprising:
a substrate having at least one semiconductor layer; a shallow trench isolation area; an oxide layer formed over said substrate and said shallow trench isolation area; a floating gate layer formed over said oxide layer; and at least one polysilicon structure formed above and adjacent to said oxide layer, said at least one polysilicon structure is adapted to increase capacitive coupling of said memory device.
- 38. The computer system of claim 37 wherein said at least one polysilicon structure is selected from the group consisting ears and wings.
- 39. The computer system of claim 37 wherein said at least one polysilicon structure is a pair of ears formed over the floating gate layer in proximity of, but not in contact with the oxide layer.
- 40. The computer system of claim 37 wherein said at least one polysilicon structure is a pair of wings formed adjacent to said floating gate layer and over a portion of said oxide layer.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a division of U.S. patent application Ser. No. 09/808,484 filed Mar. 14, 2001.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09808484 |
Mar 2001 |
US |
Child |
10273053 |
Oct 2002 |
US |