Claims
- 1. A method of making a semiconductor device fuse, comprising:forming a dielectric material layer on at least a portion of a fuse material, the dielectric material layer having a first region overlying a portion of the fuse material to be blown and a second region bounding the first region; depositing and patterning a photoresist mask on at least a portion of the dielectric material such that the second region of the dielectric material is exposed; removing a portion of the dielectric material in said exposed patterned region to reduce the thickness of the dielectric in the patterned region, such that the reflectance of incident laser light from said dielectric in the first region is less than that from the dielectric in the second region; and removing the photoresist mask.
- 2. The method of claim 1, wherein said fuse material comprises polysilicon.
- 3. The method of claim 1, wherein said fuse material comprises a metal.
- 4. The method of claim 3, wherein said metal is one of Al, AlCu, Cu and W.
- 5. The method of claim 1, wherein said dielectric comprises at least one of SiO2, Si3N4, SiOxNy(Hz), CaF2, and polyimide.
- 6. The method of claim 5, wherein said dielectric is SiO2.
- 7. The method of claim 1, wherein said dielectric removal is accomplished by an etching process.
- 8. The method of claim 7, wherein said by etching process comprises RIE.
- 9. The method of claim 7, wherein said by etching process comprises BOE.
CROSS-REFERENCE TO RELATED APPLICATIONS
This is a Divisional application of copending prior application Ser. No. 09/118,231 filed on Jul. 17, 1998, the disclosure of which is incorporated herein by reference.
This application is related to co-pending U.S. patent application Ser. Nos. 09/118,602, 09/118,232 and 09/118,230 filed concurrently herewith, which are incorporated herein by reference for all purposes.
US Referenced Citations (19)
Non-Patent Literature Citations (3)
Entry |
Smith, Robert T., et al., “Laser Programmable Redundancy and Yield Improvement in a 64K DRAM,” IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, pp. 506-513 (Oct. 1981). |
Kantz, Dieter, et al., “A 256K DRAM with Descrambled Redundancy Test Capability,” IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 596-601 (Oct. 1984). |
John Wiley & Sons, Ltd, “Redundant Circuits for Enhanced Yield,” Semiconductor Memories, S. Ed, p. 201 (1991). |