Patent Application
20050082583
The present invention relates to the self-alignment of a V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
V0-contacts are contact vias which are used as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. In prior art FeRAM memories, in order to simplify process development, a huge space is designed in between the V0-contact and the capacitor side wall to avoid shorts and capacitor damage.
A TW-contact 205 extends through the cover layer 201, TF-mask 105, and the encapsulation layers 215, 216, to provide an electrical connection to a top electrode TE 207.
A CS-contact 223 provides a contact to the source/drain of a CMOS device. A V0-contact 221 passes though a dielectric covering 222 and connects electrically to th CS-contact 223. As can b s en, there is a huge space between th V0-contact 221 and a capacitor stack contact 223, making the memory chip 200 large. In the prior art, despite the cover and encapsulation layers, this huge space has been necessary to prevent short circuits and capacitor damage.
It would be desirable to reduce the size of the memory cell and overall FeRAM chip without the resulting short circuits or capacitor damage.
The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A is method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a boftom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
Further preferred features of the invention will now be described for the sake of example only with reference to the following figures, in which:
The present invention provides self-alignment of the V0 contact in a FeRAM memory cell for reduction in the size of the memory cell.
The process flow is as follows:
a) Encapsulation of the capacitor 213 is performed as early and as is well as possible. One encapsulation layer 216 (solid line) is deposited over the TE 207 before depositing the TE-mask so that it is under the TE-mask, and the encapsulation layer 415 is deposited before depositing the BE-mask 107 so that it is under the BE-mask 107 as is currently done. The TE-mask can be made of TEOS, TiN or other metal, oxide or nitride materials, for example, and can be deposited using such methods as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), or atomic layer deposition (ALD).
b) The BE-electrode 209 is then etched as steeply as possible and the cover layer 403 is deposited. Next the dlelectric layer 222 is applied. To protect the capacitor and bottom electrode during etching of the hole for a V0-contact 405 through the layer 222, the cover layer 403 serves as both an etch stop liner and as a cover. A highly selective etch is used which stops on the cover layer 403. Due to the effect of the spacer, the cover layer 403 remains intact on BE-sidewalls 407. The result is almost vertical BE sidewalls 407, good step coverage for the ALD-deposition of Alumina inside the V0-contact hole 405, highly selective etch of the hole for the V0-contact 405, and no “noses” (no “noses” means that the sidewalls of the V0-contact hole 405 are smooth), thus providing a good Alumina spacer deposited on the walls of the V0-contact hole 405.
c) A break-through etch is next used to clean the bottom of the V0-contact 405 and creates an electrical contact with the CS-contact 223 underneath.
This process can be used even when the TE 207 and BE 209 are etched together.
This process also works well with dry etching techniques.
Still other materials and method steps can be added or substituted for those above. Thus, although the invention has been described above using particular embodiments, many variations are possible within the scope of the claims, as will be clear to a skilled reader.
