Self-calibrating operational amplifier

Abstract

A stable, reliable, op-amp circuit overcomes the adverse affect of input offset voltages, VOSI, present at the input of op-amp. In one application, such VOSI-compensated op-amps employ a standard bandgap voltage input to achieve an improved voltage regulated reference source. A new circuit combination includes an auto-zero circuit arrangement intermediate an input network and the op-amp exhibiting the input voltage offset. In an auto-zero mode, the new auto-zero circuit arrangement samples the op amp's VOSI and redistributes the sampled signal in a storage network for use in compensating for the VOSI while operating in a normal mode. As the potential for VOSI problems again develops, another auto-zero pulse causes the circuit arrangement to switch again to the auto-zero mode and the cycle continues. Because the auto-zero arrangement employs the actual VOSI encountered in a specific op-amp, and that value for VOSI is used to null the error-causing input, the circuit arrangement is self-calibrating. If changes in environmental conditions tend to cause a particular VOSI to be encountered, then it is that value for VOSI that is nulled.

Description

FIELD OF THE INVENTION

The present invention relates to solid state devices and methods for providing accurate voltage reference sources. More particularly, the present invention relates to devices, circuits and methods for providing bandgap voltage reference sources. Still more particularly, the present invention relates for devices, circuits and methods for providing simple low-cost bandgap voltage reference sources for use in applications such as analog-to-digital (ADC) digital-to-analog (DAC) and temperature measuring circuits and systems.

BACKGROUND OF THE INVENTION

Solid-state temperature sensors are widely used to provide reliable temperature measurement for many applications. In fact, silicon sensors often provide superior performance at a much lower cost than resistance-temperature-detectors, thermocouples and thermistors. Silicon-based temperature measurement typically involves an integrated circuit (hereinafter “IC”) and a sensor diode as shown in FIG. 1 . The IC 100 in FIG. 1 applies current to diode 150 using on-chip current sources 110 and 115 of standard design and corresponding switches S 1 and S 2 ( 120 and 125 , respectively). Clock and switch control circuit 140 provides alternating clock control signals to alternately close switches S 1 and S 2 and apply the respective currents to diode 150 . Measurement circuit 130 then measures the voltages, V BE , appearing across the diode when the currents are applied, which voltage is proportional to temperature. Specifically, switch control circuit 140 is shown generating the alternating sampling signals, Φ 1 and Φ 2 . During clock phase 1 , Φ 1 , switch S 1 is closed and the diode is biased by I 1 to produce a voltage, V BE1 . During clock phase 2 , Φ 2 . switch S 2 is closed and the diode is biased by I 2 to produce voltage, V BE2 . The measurement circuit samples and stores the diode voltage during each clock phase.

The measurements are based on a diode's voltage-current relationship, which is governed by the equation

 V BE =V T *ln(I D /I s )  (1)

where, I D is the forward diode current, I S is the diode reverse-saturation current, V BE is the forward diode voltage, and V T is the diode's thermal voltage given by

V T =K*T/q  (2)

where, K=Boltzmann's Constant=1.38066*10 −23 J/° K

T=Temperature in degrees Kelvin, ° K, and

q=Electron Charge=1.602*10 −19 Coulombs.

It can be shown that the change in voltage measured across a diode, ΔV BE , when the diode is excited with two different currents, I 1 and I 2 , is

ΔV BE =V T *ln(I 1 /I 2 )  (3)

Equation (3) is based on the assumption that the diode is operating in its linear, 60 mV/decade (Gummel-Poon) region. If the currents, I 1 and I 2 , are precisely matched, then ΔV BE can be used to provide a very stable, well-defined thermometer signal by substituting Equation (2) in Equation (3) and solving Equation (3) for T.

FIG. 1 illustrates a “single-wire” diode temperature measurement system in which only one conducting path connects a single pin of IC 100 and diode 150 . The structure of FIG. 1 can, of course, be expanded for use with a plurality N of diodes, each connected to a respective pin on an IC such as 100 in FIG. 1 , and each monitoring temperature at a respective off-chip location. A standard N:1 multiplexer is then controlled by the clock and control circuit 140 to connect the measurement circuitry 130 to each of the N diodes in turn.

By way of contrast, FIG. 2 illustrates the use of a transistor 250 to provide a more accurate “two-wire” differential measurement. The IC 200 in FIG. 2 contains an excitation circuit comprising current sources I 1 ( 215 ), I 2 ( 210 ), and respective switches S 1 ( 220 ), and S 2 ( 225 ), operating under the control of clock and switch control circuit 240 , as in FIG. 1 . Again, the voltages V BE1 and V BE2 are sampled and stored. The two-wire connection of transistor 250 (which may be a PNP or NPN transistor) to IC 200 includes the ground sense path 270 connecting the base of transistor 250 to ground pin at IC 200 . Because of the transistor connection, the current flowing in the ground sense wire is divided by the β of transistor 250 . Also, in the circuit of FIG. 2 current flows from the excitation circuit output through pin 245 of the IC 200 and through a wire connection 260 having resistance R WIRE to the emitter of transistor 250 . If the resistance of the wire 260 causes an excessive voltage drop, then it may be desirable to provide a second conducting path 265 connecting the emitter to the IC measuring pin. Multiplexing techniques can be applied to the circuitry of FIG. 2 in the same manner as for the diode monitor arrangement of FIG. 1 . Either PNP or NPN sensor transistors can be used in such applications.

If the currents I 1 and I 2 in the circuits of FIGS. 1 and 2 are precisely in the proportion I 1 =M*I 2 , and the measurement circuit is designed to subtract V BE2 from V BE1 , then the residual signal, ΔV BE =V T *ln(M), provides an accurate measure of temperature. A key to achieving accurate temperature measurement using this technique therefore is the matching of the current sources, I 1 and I 2 . It is generally not possible to exactly match two independent current sources on a chip with any high degree of reproducibility.

Ratio matching in the range of 0.1% to 1.0% can be achieved through the use of very precise design and manufacturing techniques, but many applications require better accuracy. One-time factory calibration is often used to reduce the current source mismatch error, but this approach relies on the use of expensive manufacturing techniques including thin-film laser trimming, so-called zener-zapping, or fuse blowing. These solutions require additional active silicon for implementation, which increases the size and cost of the chip. Furthermore, the extra trim circuitry and testing results in a reduction of product yield and increase in manufacturing cost.

Central to many prior art temperature measurement systems of the type described above is a stable, reliable, robust voltage reference. Classic bandgap voltage references are described, e.g., in, Horowitz, P and W. Hill, The Art of Electronics, 2 nd Ed., Cambridge Univ. Press, 1989, especially pp. 335-339. Input offset voltages, V OSI , present at the input of op-amps used in standard bandgap voltage references introduce errors that can prove troublesome for many applications. As with other operational amplifiers (op-amps) and other analog circuit designs, means are often provided to trim or otherwise adjust imbalances and variations encountered in particular integrated circuit (IC) implementations of bandgap references. The design and manufacturing complexities of introducing such trimming and adjusting proves to be time consuming, wasteful of IC device area and generally more costly.

SUMMARY OF THE INVENTION

The limitations of the prior art are overcome and a technical advance is made in accordance with the present invention as described in illustrative embodiments herein.

In accordance with an illustrative embodiment of the present invention, a new auto-zero circuit arrangement is provided intermediate, an input network—such as a standard reference diode network—and an op-amp exhibiting an input voltage offset, V osi . This combination provides a voltage reference solution for sampled data systems that avoid prior art limitations. In response to a periodic “auto-zero pulse,” the new auto-zero circuit arrangement nulls the op amp's V OSI while functioning in an “auto-zero” mode. After the auto-zero circuit returns to its normal mode, the overall combination is then in condition to function without the troublesome V OSI effect. As the potential for V OSI problems again develops, another auto-zero pulse causes the circuit arrangement to switch again to the auto-zero mode. The frequency and duration of auto-zero pulses can be chosen to meet the requirements of particular applications and op-amp designs.

Because the auto-zero arrangement employs the actual V OSI encountered in a specific op-amp, and that value for V OSI is used to null the error-causing input, the circuit arrangement is self-calibrating. If changes in environmental conditions tend to cause a particular V OSI to be encountered, then it is that value for V OSI that is nulled.

The illustrative auto-zero self-calibrating bandgap voltage reference source is disclosed in the context of a temperature measurement application of the inventive contribution, but no such application should be interpreted as a limitation on the scope of the present claimed invention. Rather, the self-calibrating techniques of the present invention will find application in a wide variety of op-amp circuits.

BRIEF DESCRIPTION OF THE DRAWING

The present invention will be understood more fully after a consideration of the following detailed description in connection with the attached drawing wherein:

FIG. 1 illustrates a prior art use of an integrated circuit and a diode to measure temperature.

FIG. 2 illustrates another prior art temperature measuring combination using a transistor-integrated circuit diode to measure temperature.

FIG. 3 illustrates a general switched-current-source excitation and measuring circuit used in combination with a sensor in accordance with one context for use of embodiments of the present invention.

FIG. 4 shows an illustrative sigma-delta analog-to-digital converter (ADC) for use in combination with embodiments of the present invention.

FIGS. 5A-E show typical waveforms associated with illustrative modulator operation in accordance with embodiments of the present invention.

FIG. 6 shows an illustrative combination circuit embodying an application of the present illustrative embodiment with aspects of the circuitry of FIGS. 3 and 4 above and a multiplexer used with one or more sensors.

FIG. 7 shows an illustrative analog-to-digital converter error correction circuit for use with embodiments of the present invention.

FIG. 8 shows a well-known prior bandgap voltage reference.

FIG. 9 shows an illustrative embodiment of a self-calibrating bandgap voltage reference in accordance with aspects of the present invention.

FIGS. 10A and 10B illustrate typical waveforms of control signals used in respective modes of operation of the circuit of FIG. 9 .

FIG. 11 shows a circuit representation illustrating a first mode of operation of the circuit of FIG. 9 .

FIG. 12 shows a circuit representation illustrating a second mode of operation of the circuit of FIG. 9 .

FIG. 13 shows a generalized single-ended calibration circuit using principles embodied in the circuit of FIG. 9 .

FIG. 14 shows a generalized differential calibration circuit using principles embodied in the circuit of FIG. 9 .

DETAILED DESCRIPTION

Initially, a temperature measurement arrangement will be described as an example of the application of an illustrative voltage reference source in accordance with aspects of the present invention.

Temperature Measurement

A solution to the problem of current source mismatching is depicted in illustrative embodiment in FIG. 3 . Instead of employing the prior art technique of using two current sources (one unit size source and one relatively large size source) to generate ΔV BE , a plurality, M, of unit-size current sources are used. Current sources, I 1 to I M , and corresponding switches S I to S M operate sequentially under the control of respective control signals from clock and switch control circuit 340 , thereby to limit current source mismatch error to an insignificant level. In particular, each current source can be expressed as I u +e j , where e j represents a random mismatch error due to process variations and imperfections. A switch control system operating, e.g., under a repetitive M-cycle two-phase clock represented by outputs of clock and switch control circuit 340 is advantageously used to sequentially apply the output of each of the currents sources I 1 , I 2 , . . . , I M to sensor 350 . Sensor 350 may again be a diode (as in FIG. 1 ) or a PNP or NPN transistor (as in FIG. 2 ). Dashed line 360 is used to represent the additional connection that is associated with use of a transistor rather than a diode.

As each current source is selected and its output applied to sensor 350 , the voltage V BE corresponding to the voltage drop across the diode or base-emitter junction of the sensor, as the case may be, is advantageously measured and stored. When all M voltages are measured and stored, the average, V BE(AVG) , of the voltage samples is determined. It proves advantageous when making the voltage measurements and determining the average, to also measure and store the diode voltage, V BE(TOT) , with all switches closed simultaneously, and then subtract V BE(AVG) from V BE(TOT) . Thus,

V BE(AVG) =V T *ln{I AVG /I S }=V T *ln[(M*I u +Σe j )/(M*I S )]  (4)

V BE(TOT) =V T *ln[(M*I u +Σe i )/I S ].  (5)

Equations (4) and (5) can be combined, to obtain the desired difference

ΔV BE =V T *ln(M).  (6)

Equation (6) is then solved for T after substituting for V T using Equation (2). The temperature variable, T, is thus found to be in direct proportion to ΔV BE , with the proportionality factor depending only on the constants K and q and the parameter M. Using this approach to generate a signal proportional to temperature permits the designer to achieve a result that is insensitive to process variations and device mismatches, thus creating a circuit design that is robust and portable to many manufacturing contexts and circuit contexts. While a particular circuit arrangement for converting the analog measurement signals to a convenient digital form will be described below, switched current source excitation and measurement circuits based on the illustrative embodiment shown in FIG. 3 may take many and varied forms.

Moreover, the above-described switched current averaging design provides high frequency noise immunity critical in applications such as computers, communications, automotive and industrial control equipment. Significantly, no factory calibration or trimming is required, thereby reducing chip size and manufacturing cost. As in the discussion of the circuits of FIGS. 1 and 2 , a single IC can be used to measure temperature at several locations within a system by simply switching the excitation and measurement circuitry through a multiplexer to each of several remote sensors (diodes or transistors). This is shown in FIG. 6 , which will be described more completely below.

To better understand the operation of the circuit of FIG. 3 in generating analog signals related to the temperature at one or more sensors such as diode 350 , and to provide an introduction to the conversion of these signals to a digital representation proportional to that temperature, it proves useful to consider a particular example with reference to Table 1. In that table, there is referenced in the left hand column cycles of a repetitive clock signal of the general form shown in FIG. 5 A and appearing as an output in clock and switch control circuit 340 in FIG. 3 . Non-overlapping clock phases Φ 1 and Φ 2 having the form shown in FIGS. 5B and 5C , respectively, are likewise shown as outputs of clock and switch control circuit 340 .

The center column in Table 1 shows switches closed during Φ 1 of each clock period, while the right column shows switches closed during Φ 2 of these clock periods. As can be seen, each of the switches S 1 through S M is closed in sequence during Φ 2 of a respective clock cycle, thereby causing corresponding currents I 1 through I M to be applied to sensor 350 in the circuit of FIG. 3 . By contrast, all of the switches S 1 through S M are closed during each Φ 1 , and all of currents I 1 through I M are applied to sensor 350 during each Φ 1 . It proves convenient to refer to the voltages measured by measurement circuit 330 in FIG. 3 during each Φ 1 and Φ 2 as V BE(Φ 1 ) and V BE(Φ 2 x) , respectively.

TABLE 1
	SWITCHES CLOSED	SWITCHES CLOSED
CLOCK CYCLE	DURING Φ 1	DURING Φ 2
1	S 1 through S M	Only S 1
2	S 1 through S M	Only S 2
3	S 1 through S M	Only S 3
***	***	***
M	S 1 through S M	Only S M
M + 1	S 1 through S M	Only S 1
***	***	***

Since there are M current sources switched by M switches under the control of a periodic two-phase clock, this sequence repeats until the conversion is complete. It will be noted below in connection with an illustrative temperature-to-digital conversion circuit that the M-clock-cycle sequence of Table 1 is advantageously repeated for 2 n+1 clock cycles to achieve an n-digit representation of ΔV BE , which has been shown to be proportional to temperature. Upon scaling of the proportionality constant in standard fashion, the n-digit representation will report temperature at sensor 350 .

Temperature-to-Digital Conversion

As noted above, the voltage signals measured upon application of the various currents by applying the switches in FIG. 3 are analog signals. A sigma-delta (ΣΔ) analog-to-digital converter (ADC) is advantageously used to accurately convert these analog voltages to digital values. An illustrative ΣΔ ADC is shown in the circuit arrangement of FIG. 4 . In particular, that circuit proves useful in generating digital values for ΔV BE described above in connection with Equation (6). Though an illustrative ΣΔ ADC is shown in FIG. 4 for measuring ΔV BE , it will be recognized that other ADC arrangements, and other particular ΣΔ ADCs will prove useful in combination with other elements of the present invention.

Using the architecture of FIG. 4 power requirements and required device area are modest, thus favoring implementation as part of an IC without imposing stringent processing requirements. For definiteness, the following discussion of the illustrative sigma-delta ADC shown in FIG. 4 is based on analog input signals reflecting voltages appearing at a sensor diode resulting from the application of currents from the switched current source arrangement shown in FIG. 3 , with currents applied in accordance with the example of Table 1. As discussed above the sensor 350 may be a transistor in appropriate cases.

The illustrative circuit of FIG. 4 can be seen to include four main sections: a switched-capacitor (S-C) integrator including an operational amplifier (op amp) 400 , a comparator 410 , switch control logic 420 and a 1-bit digital-to-analog converter (DAC). The 1-bit DAC is realized through the combination of switches S 4 -S 8 and C 3 connected in the circuit in the manner shown in FIG. 4 . Such 1-bit DACs are common in sigma-delta ADCs

Since the signals representing temperature usually change slowly, a first-order modulator is used to convert the input voltages into a stream of pulses having a count that is proportional to temperature at sensors such as 350 in FIG. 3 . Counter/decimator 430 receives, decimates and filters the pulse stream output from comparator 410 via switch logic circuit 420 to record the digital representation of the differential voltage ΔV BE . Such decimating and filtering are well-known in the art for use with ΣΔ ADC's of the general type shown in FIG. 4 and will not be detailed further in the present description. Typical use of such decimation filtering operations in conjunction with ΣΔ ADCs and related circuits is illustrated, e.g., in U.S. Pat. Nos. 4,972379; 4,972,436; 5,051,981; 5,157,395; and 5,646,621, though none of these specific designs is uniquely related to the present invention and embodiments thereof.

The S-C integrator comprises switches S 1 through S 3 , S 9 , and capacitors C 1 and C 2 . These switches and capacitors are of standard design and will typically be implemented with building block elements characteristic of the IC device design. The S-C integrator operates on a clock signal having the illustrative form shown in FIG. 5A , which clock signal is shown as an input to switch logic circuit 420 in FIG. 4 . This clock signal has two non-overlapping clock phases, Φ 1 and Φ 2 , shown in FIGS. 5B and 5C , respectively. It proves convenient to derive two additional clock signals (not shown) from Φ 1 , one being 1 only when Φ 1 and the output of comparator are 1, and the other being 1 only when Φ 1 is 1 and the output of comparator 410 is 0. Reset signal Φ RESET is applied to close switch S 9 across C 2 at the beginning of an entirely new measurement cycle, the effect being to initially bias op amp 400 to an operating point which will avoid saturation of the op amp during its operation.

In one specific embodiment, the complete temperature-to-digital conversion employs 2 n+1 cycles of the clock signal shown in FIG. 5A , where n is the number of desired digital output (result) bits. During each Φ 1 portion of the clock cycle, shown in FIG. 5B , C 1 samples V BE(Φ 1 ) , and during clock Φ 2 , C 1 samples V BE(Φ 2 ) , with (V BE(Φ 1 ) >V BE(Φ 2 ) ). As was discussed above in connection with Table 1, V BE(Φ 1 ) and V BE(Φ 2 ) correspond to signals generated as the switched current sources are applied (in illustrative fashion as indicated in Table 1) to sensor 350 in FIG. 3 . For the example described above, these illustrative signals correspond to V BE(TOT) (during Φ 1 ) and V BE(AVG) (during Φ 2 averaged over the measurement cycle), respectively. Of course the arrangement of FIG. 4 can be applied to ADC operations generally. For example, these techniques can be used not only for temperature measurement, but in providing a digital output in response to applied differential voltages of many kinds. When one of the inputs is held at any fixed potential, subject to V IN(Φ 1) >V IN(Φ 2) , the circuit of FIG. 4 functions as an accurate digital differential voltmeter.

In typical operation, the cycle of signals generated by the application of current sequences shown in Table 1 will be repeated many times for each n-digit output from decimation filter 430 . Different values for the parameters M and n, as well as the particular design chosen for filter 430 will generally affect the number of clock cycles for each new output. Some detailed designs permit a result after as little as M periods. When the switched current excitation arrangement and voltage measurement circuitry are multiplexed among C sensors 640 - 1 through 640 -C as shown in FIG. 6 , the period between available output readings for a particular sensor will be increased accordingly.

Returning to the operation of the modulator of FIG. 4 , it is seen that this arrangement operates, in one aspect, as a closed-loop negative feedback system seeking to maintain an average voltage of V ref at the output of the integrator (output of operational amplifier 400 ). During Φ 1 of each clock cycle, capacitor C 1 samples V BE(Φ 1 ) on its bottom plate (via S 1 ) and V ref on its top plate (via S 2 ). Meanwhile, C 3 samples either ground via S 4 (if comparator=1) or V ref via S 5 (if comparator=0) on its bottom plate, and V ref on its top plate via S 7 . During Φ 2 of each clock cycle, C 1 and C 3 sample V BE(Φ 2 ) and V ref on their respective bottom plates while their top plates are forced to V ref by the virtual connection between the op amp's input terminals. It will be understood that the input V BE represents the output from the switched current source arrangement of FIG. 3 , with values presented at that input during respective clock phases Φ 1 and Φ 2 illustratively reflecting V BE(TOT) (during Φ 1 ) and the individual VBEs, respectively. The averaging effect of the modulator operation produces from the individual V BE arising from the application of individual current sources during their respective periods (as provided in Table 1, for example) the equivalent of V BE(AVG) being applied during the entire modulator cycle.

This architecture does not suffer from “top-plate” switching errors, which plague many designs. This is so because the voltage on the top plate of both sampling capacitors, C 1 and C 3 , is always forced to the same potential, V ref , throughout the conversion.

If V BE(Φ 1 ) is greater than V BE(Φ 2 ) , then during Φ 2 , the output of the integrator will increase as a result of the charge transfer from C 1 to C 2 . If the bottom plate of C 3 sampled 0 V during Φ 1 , then during Φ 2 , the charge transfer from C 3 to C 2 will produce a net decrease at the integrator's output. If the bottom plate of C 3 sampled V ref during Φ 1 , then no charge will be transferred from C 3 to C 2 during Φ 2 , and the integrator's output will increase based only on the transfer of charge from C 1 to C 2 .

A staircase shape waveform will typically appear at the output of integrator 400 , as shown in FIG. 5 D. This output increments upward on each clock cycle until it crosses the comparator input threshold, V ref , giving rise to the illustrative pulse shown in FIG. 5 E. The integrator output is then offset downward due to the sampling of −V ref at C 3 during Φ 1 when the comparator output is 1 (high).

If the output is initialized at V ref , then it can be shown (e.g., through charge conservation and superposition theory) that at the end of 2 n+1 clock cycles the output of the integrator is

V OUT =V ref +2 n+1 *ΔV BE *C 1 /C 2 −N*V ref *C 3 /C 2   (7)

where,

N=Number of pulses (clock cycles) during which the comparator output is high (comp=1);

n=Number of required digital output (result) bits;

V REF =Reference voltage for ADC;

C 1 =Input voltage sampling capacitor;

C 3 =V ref sampling capacitor (or 1-bit DAC).

Equation (7) can be solved for N

N=2 n+1 *(ΔV BE /V REF )*C 1 /C 3 +e  (8)

where, +1<e<−1, is the quantization error or noise of the ADC. Although C 2 does not appear in Equation (8), it controls the output voltage range of the op amp. The value of C 2 is advantageously chosen to bias the output of op-amp 400 within its linear region. A typical application of a temperature measurement system might require a 10-bit result, so 2 11 or 2048 clock cycles would typically be required for such a conversion.

The circuit in FIG. 6 combines the diode excitation circuit of FIG. 3 , shown as 610 , with the example ADC of FIG. 4 , shown as 620 , to provide a single IC chip solution to meet many temperature measurement requirements. Also presented in the circuit of FIG. 6 is a voltage reference 625 for providing the V REF voltage used in measurement circuit 620 . More will be said below about desirable implementations for voltage reference circuit 625 . The addition of C: 1 multiplexer 630 in FIG. 6 provide measurements for voltages generated at each of diodes 640 -i, i=1,2, . . . , C, when current sources are applied in the illustrative manner shown in Table 1. It again proves convenient to use a clock having two non-overlapping phases in the manner of FIGS. 5B and 5C to control switches S 1 , . . . , S M .

For the multiplexing case (i.e., where C>1), the process of applying currents in the manner of Table 1 and analog-to-digital conversion with circuit 620 is repeated for each of the C diodes shown in FIG. 6 , thereby to generate C results N j j=1, 2, . . . , C, each proportional to the temperature of a respective diode 650 -j. In one embodiment using such multiplexing techniques and circuits, the multiplexer will be on the same IC as the excitation and measuring circuitry. This would typically involve a separate excitation/input voltage pin (such as 245 in FIG. 2 ) on the IC for each temperature (or voltage) to be measured. (Of course an extra input pin can be used for transistor sensors.) In an alternative arrangement, the IC continues to use but a single pin, even when C different inputs are being measured. In such cases, an external multiplexer is used to sequentially apply the excitation signals from the IC to the sensors, and the V BE signals from the sensors to the measurement circuitry on the IC. As always, a second pin may be required when using a transistor sensor.

It will be recognized that the circuitry of FIGS. 4 and 6 as described above, provides direct temperature-to-digital conversion with simple low-cost building blocks and standard processing techniques. The design proves to be robust and portable, in part because of its tolerance to IC process variations and imperfections. S-C integrator arrangements illustrated above are insensitive to stray capacitance and switching related errors, e.g., clock feed through and charge injection. The “top-plate” switching errors found in many S-C integrators is advantageously avoided in designs based on the above-described principles. Because sigma-delta designs based on the above principles provide averaging such designs will be found to be immune to high frequency noise found in many application environments, including computers, cellular phones, automobiles, etc. As noted in connection with the switched-current source elements described earlier, those skilled in the art will find that factory calibration and trimming can readily be avoided using the present design principles and embodiments. Avoiding such additional processing and structures helps reduce IC chip size and manufacturing cost.

Analog-to-Digital Converter Error Correction

While the analog-to digital circuits described above have high reliability and accuracy suitable for many applications, certain errors common to all sampling systems may warrant further treatment in some cases. For example, switching errors can occur due to charge injection and clock feed through in the S-C integrator of FIG. 4 . These switching errors can usually be remedied by using non-overlapping clocks to minimize clock feed through errors, and by using sufficiently slow fall times on clock edges to reduce charge injection errors.

So-called “offset errors” related to the input offset voltage, Vos 1 , of the integrator op amp 400 in FIG. 4 are also of concern. See, for example, Horowitz, P and W. Hill, The Art of Electronics, 2 nd Ed., Cambridge Univ. Press, 1989, especially Chap. 4 Feedback and Operational Amplifiers. V OSI errors typically arise from signal path device mismatches inside an op amp caused by imperfections in the manufacturing process. These errors can be calibrated by using the well-known trimming techniques noted above. However, use of trimming and related solutions usually increases complexity and cost of manufacturing IC products, and does not eliminate errors resulting from normal variations in temperature, power supply voltage or common-mode input voltage.

In accordance with another aspect of the present invention, therefore, low frequency offset related errors and noise are substantially eliminated in the analog-to-digital (ADC) architecture presented above with minimal impact on the chip size or power consumption. This result will obtain in the specific use of the ADC to measure temperature, but also more generally in application of ADCs for measuring voltage i.e., with ΔV BE replaced with a general input voltage V IN .

Two measurement periods are advantageously used to eliminate low frequency errors in accordance with this aspect of the present invention. The first period provides error measurement and the second period provides signal measurement. For temperature measurement applications, the operation of the modulator will follow the detailed description given above in connection with FIGS. 3-6 , except that during the error measurement period, V BE is the same during both Φ 1 and Φ 2 . This is conveniently accomplished by selecting one of the current sources in the illustrative switched current excitation circuitry of FIGS. 3 and 6 to bias the sensor diode throughout the entire error measurement period, instead of cycling and sequencing through the switches. The selection is accomplished with straightforward logic circuitry appropriate to the logical building blocks used in designing and manufacturing the IC on which correction is to be accomplished. Such logic circuitry is well-known in the art and will not be detailed here.

In error measurement periods for more general voltage measurement applications, the bottom plate of C 1 in the illustrative circuit of FIG. 4 is connected to any stable reference point (e.g. ground or Vref) during both Φ 1 and Φ 2 .

Op amps can have either positive or negative V OSI errors. Thus, in order to maintain negative feedback in the modulator loop circuits such as that of FIG. 4 , a small positive input voltage≧V OSI , (referred to the input) is advantageously injected. This new input signal is quantized by the ADC of the circuit of FIG. 4 during both the error measurement and signal measurement periods, and the system parameters are chosen to ensure that the modulator does not saturate.

These above-described techniques are readily demonstrated in connection with the illustrative circuit of FIG. 7 . There, switches S P1 and S P2 and capacitor C p are added to the S-C integrator of FIG. 4 . The integrator output will now experience an incremental positive step during each clock cycle given by

 ΔV OUT =+V ref *C p /C 2   (9)

The value of C P is chosen such that

V ref *C p /C 2 ≧V error *C 1 /C 2   (10)

where, V error represents the net input referred error due to V OSI and switching errors. Now, during the error measurement period, the modulator will produce a count

N EM =N p +N e   (11)

where,

N P =2 n+1 *(V ref /V ref )*C p /C 3 =2 n+1 *C P /C 3   (12)

and

N e =2 n+1 *(V error /V ref )*C 1 /C 3   (13)

During the signal measurement period, the modulator will produce a count

N SM =N VIN +N p +N e   (14)

where, N VIN is the number of counts proportional to the input signal. In equation (14), N VIN and N P are always positive, while N e could be either positive or negative. The net result, N T , which is calculated by subtracting N EM from N SM

N T =N SM −N EM =(N VIN +N P +N e )−(N P +N e )=N VIN   (15)

is exactly proportional to the input and all low frequency errors have been eliminated. The subtraction function can be easily implemented in silicon by using an up-down counter or by using an up counter and two's complement addition.

One illustrative arrangement based on an up-down counter is shown in FIG. 7 where the comparator, clocking and logic circuitry described above in connection with FIG. 4 is represented by block 720 . Likewise, the operative function of decimator 430 in FIG. 4 for purposes of understanding the illustrative error-correcting functionality is represented by reversible (up-down) counter 730 . Counter 730 is arranged to receive pulses output from the comparator/logic circuitry 720 reflective of the several voltages appearing at the output of op-amp 710 and to register these as counts. In the zero-differential-input error measurement mode (mode 1 in FIG. 7 ), the counts that appear are those reflective of the V OSI error and the injected small positive voltage at the input of the op-amp. Because the injected voltage is positive and of magnitude greater than that of V OSI , the count at reversible counter 730 is illustratively decremented during the error measurement mode (mode 1 ). Then, when the signal measurement mode (mode 2 in FIG. 7 ) is operative, the always-positive error introduced by injecting the small positive voltage (added with the smaller-magnitude, possibly negative V OSI ) is effectively canceled by having the mode 2 signals (which include these error signals) counted in the opposite direction, i.e., incremented. The order of the two kinds of measurements (errors only and signal with errors) corresponding to mode 1 and mode 2 above is not important; errors can be measured first, or last.

The errors introduced by V OSI and small positive voltage injection do not usually change over short time intervals. Accordingly, error measurements need not be performed for each overall voltage measurement cycle. Rather, once an error count is determined, it can be stored for use over many full input signal measurement intervals. The frequency of error measurement intervals can be selected based on environmental conditions or particular applications. Though the ratio of input signal measurements to error measurements can be quite large, a simple choice, is to have one error count for each input signal count.

This error correction arrangement provides tolerance to process variations and imperfections thereby making the design robust and portable. Moreover, the design can be implemented with simple, standard building block components, thereby reducing development time and manufacturing cost. Typical silicon implementations of the described error-correction circuitry occupy minimal area and consume very little power, thus making it ideal for portable and battery powered applications. Because the above described sigma-delta design inherently provides averaging, this circuit proves highly immune to high frequency noise commonly found in computers, cellular phones, automobiles, etc. The described error correction scheme removes substantially all low-frequency errors caused by temperature variations, power supply changes and S-C integrator op amp 1/f noise. As for other circuits described above, the error correction circuit features require no one-time factory calibration or trimming.

Self-Calibrated Basidgap Voltage Reference

All ADCs, and many other applications, require a stable voltage reference in order to make accurate measurements or otherwise perform within prescribed constraints. Preferably the voltage reference should provide such an accurate and stable output while consuming minimal power and operating with the lowest possible power supply voltage. One class of circuits that has found widespread use for these purposes is the so-called bandgap voltage reference generator.

The circuit shown in FIG. 8 is a bandgap voltage reference well-known in the prior art. The op amp 810 , resistors R 1 -R 2 and diodes D 1 and D 2 are configured to generate an output voltage

V ref =V BE1 +ΔV BE *R 2 /R 1 +V osi *R 2 /R 1 .  (16)

where, ΔV BE =V T *ln(M), is produced by forcing equal currents into the diodes D 1 and D 2 , whose areas are ratioed by M, i.e., the areas of D 2 and D 1 are in the ratio M:1. Typical values for the variables in equation (16) are V ref =1.2V, V BE1 =0.6V, ΔV BE =60 mV, and R 2 /R 1 =10. This circuit amplifies V OSI variations appearing across the op-amp 810 by a factor of 10 (referred to the output), which adversely effects the performance of the system. One-time factory calibration or trimming have been used in prior art circuits to combat such V OSI induced errors, but this approach suffers from the same shortcomings described above.

The circuit shown in FIG. 9 provides a voltage reference solution for sampled data systems that avoid prior art limitations. A new auto-zero circuit is added between op amp 810 and the bandgap diodes and resistors of FIG. 8 to periodically null the op amp's V OSI while functioning in an “auto-zero” mode. FIGS. 10A and 10B illustrate waveforms used for circuit operation during both normal mode and the auto-zero mode. In particular, pulses 950 and 951 in FIG. 10B are auto-zero pulses used during the auto-zero mode of operation.

Capacitors C 1 -C 4 and switches S 1 -S 6 effectively sample V OSI during auto-zero mode, Φ 2 , and redistribute the charge to cancel the error during normal mode, Φ 1 . The refresh rate for the capacitors depends on the leakage currents in the switches and size of the capacitors. For 1 pF capacitors and minimal geometry switches, the circuit will typically be refreshed at least once per millisecond in order to minimize droop on the capacitors and reduce the common-mode voltage variation at the input of the op amp.

FIGS. 11 and 12 show equivalent circuits for the operation of the improved bandgap reference circuit of FIG. 9 while operating in the normal and auto-zero modes, respectively. In FIG. 11 charge is shown being redistributed between C 1 and C 3 , and between C 2 and C 4 . (All of capacitors C 1 -C 4 are taken as equal in value.) The voltage of C 1 in parallel with C 3 and C 2 in parallel with C 4 is seen to reach V OSI with the indicated polarities in normal mode operation. In the equivalent circuit of FIG. 12 , capacitors C 3 and C 4 are shown as shorted while operating in the auto-zero mode, while capacitors C 1 and C 2 achieve the charge that is re-distributed in the next period of normal mode operation.

Use of the approach to generate a bandgap voltage reference shown in FIGS. 9-12 , in common with other new circuit arrangements described above include insensitivity to process variations and device mismatches, thus contributing to circuit robustness and portability to other particular applications. This switched-capacitor auto-zero technique provides low frequency noise immunity, so the design is insensitive to temperature fluctuations, power supply variations and electronic noise present in applications such as computers, communications, automotive electronics and industrial control. Again, no factory calibration or trimming is required, so IC chip size requirements and manufacturing cost are reduced.

Although the above description of the circuits of FIGS. 9 , 11 and 12 (and their operation under the control of waveforms such as those in FIGS. 10A and 10B ) illustrate an effective means for nulling op amp-related errors in bandgap voltage references, these self-calibration techniques will find more general application in an assortment of other op amp-based circuits. Typical op amp applications that will benefit from the present inventive teachings include, but are not limited to, inverting and non inverting amplifiers, voltage buffers, summing amplifiers, difference amplifiers, track-and-hold amplifiers, current-to-voltage converters, integrators, and filters. Moreover, the present inventive self-calibration circuit techniques are easily adapted to both single-ended and differential output op amp circuits, as will now be illustrated by reference to FIGS. 13 and 14 .

FIG. 13 shows an illustrative embodiment of a general purpose self-calibrating op amp circuit operating generally in accordance with the self-calibration principles described above and including the functionality of the circuit of FIG. 9 . More particularly, FIG. 13 , shows a self-calibrated, single-ended output op amp, 1310 , of the same general type shown in FIG. 9 , connected to an input network 1320 through a self-calibration circuit 1300 . It will be recognized, however, that the particular input circuit illustrated in FIG. 9 comprising diodes D 1 and D 2 and resistors R 1 and R 2 is merely illustrative; in general, input circuit 1320 will include circuit elements characteristic of any of the circuit applications noted above. Likewise, feedback network 1330 connecting the output of op amp 810 to the self-calibration circuit 1300 may be of any design appropriate to the application. Further, self-calibration network 1300 shown in illustrative embodiment as comprising the switches S 1 -S 6 and capacitors C 1 -C 4 of the circuit of FIG. 9 will assume many particular configurations and arrangements for the range of applications.

Overall then, the self-calibration arrangement of FIG. 13 will be seen to include self-calibration circuit 1300 connecting a general input network 1320 to an op amp 1310 , and a generalized feedback network 1330 connecting the output of op amp 1310 to the input of self-calibration circuit 1300 . To reflect the wide range of application of the self-calibration arrangements of the present invention, auto-zero switches S 1 -S 6 of FIG. 9 are shown as general purpose switching elements rather than as the MOS devices shown in FIG. 9 . In appropriate cases, the switching devices S 1 -S 6 shown in FIG. 13 may be MOS, bipolar or other semiconductor devices, or may be switches controlled optically, electromagneticlly or otherwise. Likewise capacitors (or other voltage or charge storage devices) represented in FIG. 13 by C 1 -C 4 may assume any of a variety of forms suitable for receiving the sampled offset voltage during the auto-zero mode, and for redistributing the sampled value when returned to a normal operation mode. Switch control signals, Φ 1 and Φ 2 will typically have the same general wave shapes shown in FIGS. 10A and 10B , with frequency and duration chosen to meet the requirements of specific applications.

In operation, the generalized self-calibration circuit of FIG. 13 will, again sample the particular V OSI encountered during use of the particular op-amp. This sampling is performed during the auto-zero mode by application of the Φ 2 signal, illustratively of the form shown in FIG. 10 B. Application of this pulse to the illustrative arrangement of switches shown in FIG. 13 , thereby to cause storage devices (e.g., capacitors C 1 -C 4 ) to be reconfigured in the illustrative manner of FIG. 12 . When the illustrative Φ 1 signal is present, the self-calibration circuit 1300 returns to the normal mode with the sampled voltage present on the storage device network in such manner as to cancel the V OSI characteristic of the op-amp.

The self-calibration functionality of circuit 1300 in FIG. 13 will also find application in differential output op amps. Such V OSI compensation techniques are ideally suited for many differential measurement applications, which applications often require low noise and/or high-speed operation. FIG. 14 illustrates a general purpose self-calibrating differential output op amp circuit. It will be recognized that the basic elements of the circuit of FIG. 13 are again present in the circuit of FIG. 14 . However, separate feedback networks, 1430 and 1440 , provide separate paths connecting the positive and negative outputs of op amp 1410 to respective first and second inputs of self-calibration circuit 1400 .

The differential nature of the self-calibration circuit of the present invention provides exceptional tolerance to system noise, charge injection and clock signal feed through switching errors, commonly associated with switched-capacitor circuits. The feedback and input networks shown in FIGS. 13 and 14 may include a myriad of passive and active devices types and arrangements, as will appear to those skilled in the art in light of the present inventive teachings.

While each of the novel individual circuits described herein have proven especially adapted for use together, those skilled in the art will recognize applications for the inventive contributions separate from other circuits described herein. Thus, the analog measurement techniques and circuits based on a plurality M of switched current sources exciting a sensor will find application independent of any particular analog-to-digital conversion technique. Likewise the disclosed sigma-delta ADC architecture and its error correction features will find application separately in many applications. Finally, the improved bandgap voltage reference and generalized Vosi-compensated op-amp will find application in myriad applications in analog voltage measurements, analog-to-digital conversion and otherwise.

No particular IC chip processing techniques are required to apply the above inventive teachings, nor are any particular component or parameter values required. Those skilled in the art will recognize and include a range of component and parameter values in applying the inventive teachings presented to a variety of combinations and applications.

Claims

1. A circuit comprisingan op-amp having at least two input terminals and at least one output terminal, said op-amp exhibiting a characteristic input offset voltage, VOSI, at said input terminals, at least one feedback network having an input terminal and an output terminal, said input terminal of each said feedback network connected to a respective output terminal of said op-amp, a self-calibration circuit having at least two input terminals and two output terminals, said self-calibration circuit receiving input signals and having at least one input terminal connected to an output terminal of at least one of said feedback networks, said output terminals of said self-calibration circuit being connected to respective ones of said input terminals of said op-amp, said self-calibration network comprising a substantially similar switched capacitor network connected between each of said input terminals of said self-calibration network and said inputs of said op-amp for sampling said VOSI during an auto-zero mode of operation and for storing said sampled VOSI for use in nulling said VOSI at said inputs of said op-amp during a normal mode of operation.

2. The circuit of claim wherein said op-amp has one output terminal and one feedback network connected between said output terminal and one of said input terminals of said op-amp.

3. The circuit of claims wherein said op-amp has two output terminals and two feedback networks, each said feedback network connected between a respective output terminal of said op-amp and a respective one of said input terminals of said self-calibration circuit.

4. The circuit of claim 1 wherein said input signals are voltage reference signals.

5. The circuit of claim 1 further comprising a source of first and second non-overlapping control signals, wherein said substantially similar switched capacitor networks are(i) responsive to said first control signal to sample said VOSI during an auto-zero mode of operation by accumulating charge on selected capacitors in said switched capacitor networks, and (ii) responsive to said second control signal to redistribute said accumulated charge among capacitors in said switched capacitor networks during a normal mode of operation.

6. The circuit of claim 5 wherein said capacitors in said switched capacitor networks comprise a plurality of substantially equal-value capacitors.

7. A voltage reference source comprisingfirst and second diodes providing respective different voltages VBE1 and VBE2 when stimulated by respective applied currents, an operational amplifier (op-amp) having first and second input terminals and an output terminal, said op-amp being characterized by an input offset voltage, VOSI, a circuit arrangement having first and second modes of operation positioned intermediate said first and second diodes and said op-amp for receiving and applying voltages based on said voltages VBE1 and VBE2 to said first and second input terminals of said op-amp, said circuit arrangement comprising means operative in said first mode for applying to said op-amp a voltage which nulls said VOSI during operation in said second mode.

8. A voltage reference source comprisingfirst and second diodes, providing respective voltages VBE1 and VBE2 when stimulated by respective applied currents, an operational amplifier (op-amp) having first and second input terminals and an output terminal, said op-amp being characterized by an input offset voltage, VOSI, a circuit arrangement having first and second modes of operation positioned intermediate said first and second diodes and said op-amp for receiving and applying voltages based on said voltages VBE1 and VBE2 to said first and second input terminals of said op-amp, said circuit arrangement comprising a switched capacitor network storing said VOSI during said first mode, and applying said stored VOSI to substantially cancel said VOSI at said input of said operational amplifier during operation in said second mode.

9. The voltage reference source of claim 7, further comprising means for alternating between said first and second modes of operation, said first mode of operation becoming the active mode at a time when the cancellation of said VOSI is about to deteriorate to an unacceptable level.

10. A voltage reference source comprisingfirst and second diodes, providing respective voltages VBE1 and VBE2 when stimulated by respective applied currents, an operational amplifier (op-amp) having first and second input terminals and an output terminal, said op-amp being characterized by an input offset voltage, VOSI, a circuit arrangement having first and second modes of operation positioned intermediate said first and second diodes and said op-amp for receiving and applying voltages based on said voltages VBE1 and VBE2 to said first and second input terminals of said op-amp, said circuit arrangement comprising means operative in said first mode for applying to said op-amp a voltage which nulls said VOSI during operation in said second mode, and means for alternating between said first and second modes of operation, said first mode of operation becoming the active mode at a time when the cancellation of said VOSI is about to deteriorate to an unacceptable level, said means for alternating comprising a logic arrangement responsive to an applied periodic signal, the period of said periodic signal being chosen based on the deterioration of said stored VOSI.