SELF-DETECTION CIRCUIT BASED ON POWER DETECTOR

Abstract

The present invention discloses a Self-detection circuit based on power detector, comprising a power detector, a coupler, a phased array transmitting channel 1 and a phased array transmitting channel 2, and the power detector is divided into two working modes of phase test and amplitude test. The problems that the self-test circuit is complex and large in chip area are solved.

Description

TECHNICAL FIELD

The present invention belongs to the field of advanced semiconductor technology, and in particular relates to a Self-detection circuit based on power detector.

BACKGROUND

With the diversification of the application scenarios of the phased array system, the application requirements of the phased array system in extreme environments are correspondingly higher. In the working environment of extremely high temperature and extremely low temperature, the phase control and amplitude control of the phased array system are greatly affected. Although the researchers have also conducted abundant studies on the phased array system for the application scenarios of high and low temperature, accuracy deterioration of key metrics such as phase and amplitude can never be improved very well. The phase and amplitude control accuracy is not only limited by the working environment, but also by the inconsistency of performance between channels caused by uneven heat dissipation under large-scale array integration. One of the ways to solve accuracy deterioration of the phase control module and the amplitude control module in the phased array system is to make correction, and the premise of the correction is to accurately detect the amplitude and phase information of the phased array system. Therefore, research on such problems has become a research hotspot in recent years.

At present, the existing self-test methods are mainly to couple the signal of the phased array system to the self-test link, and convert the radio frequency signal into a DC signal by mixing to zero intermediate frequency. At present, the amplitude of the quadrature I/Q two-way signal is obtained, so the orthogonality of the quadrature signal in the link is relatively high. If the quadrature signal of the link is not orthogonal enough, it will directly lead to a relatively large detected phase information error; the complexity of the self-test link is high, and the use of quadrature signal generators, mixers, driver amplifiers and other modules results in a large chip area. The existing self-test circuit has shortcomings of high complexity and a large chip area.

SUMMARY

The purpose of the present invention is to provide a self-test circuit based on the power detector, which solves the problems of high complexity and large chip area of the self-test circuit.

The following technical solutions are adopted:

• • A self-test circuit based on the power detector, comprising the power detector, the coupler, the phased array transmitting channel 1 and the phased array transmitting channel 2;
  • Among them, the power detector is divided into two working modes of phase test and amplitude test:

When the working mode is the phase test mode, the transistors Q3, Q4, Q5 and Q6 are in the cut-off state by biasing Vbias_amp=0V, and the transistors Q1, Q2, Q7, Q8 and Q9 are in the normal working state by biasing Vbias_phase=400 mV; at this time, the transistors Q1, Q2 and transistors Q7, Q8 work at the same DC bias, the four transistors are all biased at Vbias_phase, and the differential signals carrying the phase information are V+_phase and V−_phase; its voltage signals are converted into current signals through the transistors Q1 and Q2 and are carried by i_1ph and i_2ph, while V+_amp and V−_amp have no signal at this time; at the same time, under the same bias of Q7 and Q8, the corresponding DC current is i_dc, and at node A, the sum of i_1ph and i_2ph is I₁, and high-frequency signals are filtered out by cap2; current signals are converted into voltage signals through resistor R2, and the voltages at node A and node B are subtracted to obtain the DC voltage representing the phase information;

When the working mode is amplitude test, the transistors Q1, Q2, Q7, and Q8 are biased at Vbias_phase=0V, and the transistors do not work; the transistors Q3, Q4, Q5, and Q6 are biased at Vbias_amp=400 mV, and the transistors work normally; at this time, the differential signals V+_amp and V−_amp carrying the amplitude information are converted into current signals through the transistors Q3 and Q4 and are carried by the currents i_1amp and i_2amp, while V+_phase and V−_phase have no signals; the transistors Q5 and Q6 only have DC bias, and the current generated by the bias is i_dc; at node A, the sum of i_1amp and i_2amp is I₁, the high-frequency signals are filtered out by cap2, and the DC current i_dc corresponding to the transistors Q5 and Q6 is summed to be I2; the currents I₁ and I₂ are converted to DC voltage through the resistor R₂, and are subtracted to obtain the DC voltage carrying the amplitude information.

Preferably, in the phased array transmitting channel 1 and the phased array transmitting channel 2, the variable gain amplifier controls the radio frequency signal by changing the gain; the phase shifter is to change the phase of the radio frequency signal within a 360° range, and the power amplifier is to provide gain and amplify the power of the radio frequency signal to increase the transmitting power of the antenna; the amplitude and phase information of the phased array transmitting channel 1 and the phased array transmitting channel 2 is extracted to the self-test circuit through the coupler, and the power detector detects the amplitude and phase information and outputs the test voltage.

Preferably, when the working mode of the power detector is the phase test mode, the signal of the phased array transmitting channel 1 passing through the coupler is v₁=A₁ cos (ωt+φ₁), the signal of the phased array transmitting channel 2 through the coupler is v₂=A₂ cos (ωt+φ₂); the difference between the two signals through the transformer is calculated and becomes a differential signal,

$\begin{array}{cc}\Delta V=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=-2A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(1\right)\end{array}$

The differential signals are:

$\begin{array}{cc}\Delta V_{+}=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=-A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\frac{1}{2}\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(2\right)\end{array}$ $\begin{array}{cc}\Delta V_{-}=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\frac{1}{2}\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(3\right)\end{array}$

The differential signal is sent to the power detector with the amplitude detected.

When detecting the phase, the differential signal carrying the phase information enters the transistors Q1 and Q2 and is converted into currents is i_1ph, i_2ph. At the same time, Q7 and Q8 work at the same DC operating bias as Q1 and Q2; therefore, the difference between the output current I₁ of Q1 and Q2 and the output current I₂ of Q7 and Q8 is calculated:

$\begin{array}{cc}{i}_{1\mathrm{ph}}={K\left(\Delta V_{+}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(4\right)\end{array}$ $\begin{array}{cc}{i}_{2\mathrm{ph}}={K\left(\Delta V_{-}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(5\right)\end{array}$ $\begin{array}{cc}{i}_{\mathrm{dc}}+{K\left(v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(6\right)\end{array}$ $\begin{array}{cc}K=\frac{W}{2L}\mu C_{\mathrm{ox}}& \left(7\right)\end{array}$ $\begin{array}{cc}{I}_1=i_{1\mathrm{ph}}+i_{2\mathrm{ph}}& \left(8\right)\end{array}$ $\begin{array}{cc}{I}_2=2\times i_{\mathrm{dc}}& \left(9\right)\end{array}$ $\begin{array}{cc}\Delta I=I_1-I_2=2K\Delta V_{+}^2& \left(10\right)\end{array}$ $\begin{array}{cc}=2K(A_1{\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)}^2\left[1-\cos \left(2\omega t+{\phi }_1+{\phi }_2\right)\right]& \left(11\right)\end{array}$ $\begin{array}{cc}\mathrm{DC}❘\Delta I❘=2{K\left(A_1\sin \frac{{\phi }_1-{\phi }_2}{2}\right)}^2& \left(12\right)\end{array}$ $\begin{array}{cc}{V}_{\mathrm{out}}=\mathrm{DC}❘\Delta I❘\times R_2=2{K\left(A_1\sin \frac{{\phi }_1-{\phi }_2}{2}\right)}^2{R}_2& \left(13\right)\end{array}$ $\begin{array}{cc}{\phi }_1-{\phi }_2=\arcsin \left[\frac{\sqrt{V_{\mathrm{out}}/2{\mathrm{KR}}_L}}{A_1}\right]& \left(14\right)\end{array}$

The current ΔI containing the phase information is obtained, and finally it becomes the voltage information V_out through the load resistor R2; finally, a function corresponding to the difference between the phase and the output voltage is obtained, that is, formula (14); sin (φ₁-φ₂) is linearly related to √{square root over (V_out)}.

Preferably, when the power detector detects the amplitude, the signal of the phased array transmitting channel 1 passing through the coupler is v₁=A₁ cos (ωt+φ₁); the signal of the phased array transmitting channel 2 passing through the coupler is v₂=A₂ cos(ωt+φ₁); the difference between the two signals through the transformer is calculated and becomes a differential signal,

$\begin{array}{cc}\Delta V_{+}=\left(A_1-A_2\right)\cos \left(\omega t+{\phi }_1\right)& \left(16\right)\end{array}$ $\begin{array}{cc}\Delta V_{-}=-\left(A_1-A_2\right)\cos \left(\omega t+{\phi }_1\right)& \left(17\right)\end{array}$ $\begin{array}{cc}{i}_{1\mathrm{amp}}={K\left(\Delta V_{+}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(18\right)\end{array}$ $\begin{array}{cc}{i}_{2\mathrm{amp}}={K\left(\Delta V_{-}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(19\right)\end{array}$ $K=\frac{W}{2L}\mu C_{\mathrm{ox}}$ $\begin{array}{cc}{I}_1=i_{1\mathrm{amp}}+i_{2\mathrm{amp}}& \left(20\right)\end{array}$ $\begin{array}{cc}{I}_2=2\times i_{\mathrm{dc}}& \left(21\right)\end{array}$ $\begin{array}{cc}\Delta I=I_1-I_2=2K\Delta V_{+}^2={K\left(A_1-A_2\right)}^2+K\cos \left(2\left(\omega t+{\phi }_1\right)\right)& \left(22\right)\end{array}$ $\begin{array}{cc}\mathrm{DC}❘\Delta I❘={K\left(A_1-A_2\right)}^2& \left(23\right)\end{array}$ $\begin{array}{cc}{V}_{\mathrm{out}}=\mathrm{DC}❘\Delta I❘\times R_2={K\left(A_1-A_2\right)}^2{R}_2& \left(24\right)\end{array}$ $\begin{array}{cc}{A}_1-A_2=\sqrt{\frac{V_{\mathrm{out}}}{K{R}_2}}& \left(25\right)\end{array}$

When detecting the amplitude, the differential signal carrying the amplitude information sent to the transistors Q3 and Q4 are converted into currents i_1amp, i_2amp. At the same time, Q5 and Q6 work at the same DC operating bias as Q3 and Q4; therefore, the difference between the output current I₁ of Q3 and Q4 and the output current I₂ of Q5 and Q6 is calculated to obtain the current I₂ that only contains the amplitude information, and finally it becomes the voltage information V_out through the load resistance R2; a function corresponding to the difference between the amplitude and the output voltage is obtained, that is, formula (25);

When detecting the amplitude, the amplitude control unit of the phased array transmitting channel 2 is configured to the minimum gain state; at this time, the signal coupled to the power detector by the phased array transmitting channel 2 through the coupler is very small compared with the signal coupled to the power detector by the phased array transmitting channel 1, so A₂ is ignored, which is obtained from formula (25):

$\begin{array}{cc}{A}_1=\sqrt{\frac{V_{\mathrm{out}}}{{\mathrm{KR}}_2}}& \left(26\right)\end{array}$

Then, the voltage amplitude A₁ is converted to power P₁/dBm:

$\begin{array}{cc}{P}_1=10\log \left(V_{\mathrm{out}}\right)-10\log \left({\mathrm{KR}}_2\right)& \left(27\right)\end{array}$

It can be seen from formula (27) that the power P₁ is proportional to 10 log (V_out).

The beneficial effects of the present invention are as follows: the circuit of the present invention converts phase information into amplitude information by using the difference and sum of products formula, and then detects the amplitude and phase information of the phased array system through the power detector. Based on advanced semiconductor technology, the present invention converts phase information into amplitude information, and then uses the power test circuit to detect the amplitude and phase information of the phased array system; the present invention converts the phase information between the channels of the phased array system into amplitude information, and the phase test is realized through the power detector. Therefore, the circuit complexity is very low, the circuit structure is simple, and a smaller chip area is occupied.

DESCRIPTION OF DRAWINGS

FIG. 1 is the self-test architecture for phased array amplitude and phase information of the present invention;

FIG. 2 is the top view of the 3D model of the coupler of the present invention;

FIG. 3 is the oblique view of the 3D model of the coupler of the present invention;

FIG. 4 is the structure of the power detector of the present invention;

FIG. 5 is a diagram showing the relationship between √{square root over (V_out)} and sin (φ₁-φ₂);

FIG. 6 is a diagram showing the relationship between 10 log(V_out) and P₁.

EMBODIMENTS

The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the field without creative efforts shall fall within the protection scope of the present invention.

In FIG. 1, a self-test circuit based on the power detector comprises a power detector, a coupler, the phased array transmitting channel 1 and the phased array transmitting channel 2; the power detector is divided into two working modes of phase test and amplitude test.

As shown in FIG. 4, when the working mode is the phase test mode, the transistors Q3, Q4, Q5 and Q6 are in the cut-off state by biasing Vbias_amp=0V, and the transistors Q1, Q2, Q7, Q8 and Q9 are in the normal working state by biasing Vbias_phase=400 mV; at this time, the transistors Q1, Q2 and transistors Q7, Q8 work at the same DC bias, the four transistors are all biased at Vbias_phase, and the differential signals carrying the phase information are V+_phase and V−_phase; its voltage signals are converted to current signals through the transistors Q1 and Q2 and are carried by i_1ph and i_2ph, while V+_amp and V−_amp have no signal at this time; at the same time, under the same bias of Q7 and Q8, the corresponding DC current is i_dc, and at node A, the sum of i_1ph and i_2ph is I₁, and high-frequency signals are filtered out by cap2; current signals are converted into voltage signals through resistor R2, and the voltages of node A and node B are subtracted to obtain the DC voltage representing the phase information;

When the working mode is amplitude test, the transistors Q1, Q2, Q7, and Q8 are biased at Vbias_phase=0V, and the transistors do not work; the transistors Q3, Q4, Q5, and Q6 are biased at Vbias_amp=400 mV, and the transistors work normally; at this time, the differential signals V+_amp and V−_amp carrying the amplitude information are converted into current signals through the transistors Q3 and Q4 and are carried by the currents i_1amp and i_2amp, while V+_phase and V−_phase have no signals; the transistors Q5 and Q6 only have DC bias, and the current generated by the bias is i_dc; at node A, the sum of i_1amp and i_2amp is I₁, the high-frequency signals are filtered out by the capacitor cap2, and the DC current i_dc corresponding to the transistors Q5 and Q6 is summed to be I₂; the currents I₁ and I₂ are converted to DC voltage through the resistor R2, and are subtracted to obtain the DC voltage carrying the amplitude information. For the specific formula derivation, see (1)-(27).

As shown in FIG. 2, the entire large plane is the ground plane, in which the dark part is the m7 layer, and the rest is the m9 layer. The specific model is shown on the back of the pad in FIG. 3. The signal of the phased array system passes through the power amplifier, is transmitted to the Spad, and is capacitively coupled to the self-test circuit.

In the phased array transmitting channel 1 and the phased array transmitting channel 2, the variable gain amplifier controls the radio frequency signal by changing the gain; the phase shifter is to change the phase of the radio frequency signal within a 360° range, and the power amplifier is to provide gain and amplify the power of the radio frequency signal to increase the transmitting power of the antenna. The amplitude and phase information of the channel 1 and the channel 2 is extracted to the self-test circuit through the coupler, and the power detector detects the amplitude and phase information and outputs the test voltage.

As shown in FIG. 4, the power detector is mainly composed of 9 NMOS transistors Q1-Q9, and there are two working states of phase test and amplitude test. When working in phase test, the bias voltage of the transistors Q1, Q2, Q7, and Q8 is 400 mV, and the transistors work in the saturation region; the transistors Q3, Q4, Q5, and Q6 are biased at 0 mV, and the transistors are not turned on; when working in amplitude test, Q3, Q4, Q5, Q6 are biased at 400 mV, and the transistors Q1, Q2, Q7, Q8 are biased at 0 mV; the transistor Q9 is worked as a tail current source, biased at 600 mV, that is, Vbias_current=600 mV. The Capacitor cap1 is an interval capacitor whose value is 1 pF, capacitor cap2 is a filter capacitor whose value is 968 fF; resistor R1=5 kΩ and resistor R2 is a load resistor whose value is 1 kΩ. For phase information, the theoretical derivation is as follows:

The signal of the phased array transmitting channel 1 passing through the coupler is v₁=A₁ cos(ωt+φ₁); the signal of the phased array transmitting channel 2 through the coupler is v₂=A₂ cos(ωt+φ₂); the difference between the two signals through the transformer is calculated and becomes a differential signal,

$\begin{array}{cc}\Delta V=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=-2A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(1\right)\end{array}$

The differential signals are:

$\begin{array}{cc}\Delta V_{+}=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=-A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\frac{1}{2}\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(2\right)\end{array}$ $\begin{array}{cc}\Delta V_{-}=v_1-v_2=A_1\cos \left(\omega t+{\phi }_1\right)-A_2\cos \left(\omega t+{\phi }_2\right)=A_1\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)\sin \left(\omega t+\frac{{\phi }_1+{\phi }_2}{2}\right)+\frac{1}{2}\left(A_2-A_1\right)\cos \left(\omega t+{\phi }_2\right)& \left(3\right)\end{array}$

When the phase is detected, the differential signal carrying the phase information enters the transistors Q1 and Q2 and is converted into currents i_1ph, i_2ph. At the same time, Q7 and Q8 work at the same DC operating bias as Q1 and Q2; therefore, the difference between the output current I₁ of Q1 and Q2 and the output current I₂ of Q7 and Q8 is calculated:

$\begin{array}{cc}{i}_{1\mathrm{ph}}={K\left(\Delta V_{+}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(4\right)\end{array}$ $\begin{array}{cc}{i}_{2\mathrm{ph}}={K\left(\Delta V_{-}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(5\right)\end{array}$ $\begin{array}{cc}{i}_{\mathrm{dc}}+{K\left(v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(6\right)\end{array}$ $\begin{array}{cc}K=\frac{W}{2L}\mu C_{\mathrm{ox}}& \left(7\right)\end{array}$ $\begin{array}{cc}{I}_1=i_{1\mathrm{ph}}+i_{2\mathrm{ph}}& \left(8\right)\end{array}$ $\begin{array}{cc}{I}_2=2\times i_{\mathrm{dc}}& \left(9\right)\end{array}$ $\begin{array}{cc}\Delta I=I_1-I_2=2K\Delta V_{+}^2& \left(10\right)\end{array}$ $\begin{array}{cc}=2K(A_1{\sin \left(\frac{{\phi }_1-{\phi }_2}{2}\right)}^2\left[1-\cos \left(2\omega t+{\phi }_1+{\phi }_2\right)\right]& \left(11\right)\end{array}$ $\begin{array}{cc}\mathrm{DC}❘\Delta I❘\times R_2=2{K\left(A_1\sin \frac{{\phi }_1-{\phi }_2}{2}\right)}^2& \left(12\right)\end{array}$ $\begin{array}{cc}{V}_{\mathrm{out}}=\mathrm{DC}❘\Delta I❘\times R_2=2{K\left(A_1\sin \frac{{\phi }_1-{\phi }_2}{2}\right)}^2{R}_2& \left(13\right)\end{array}$ $\begin{array}{cc}{\phi }_1-{\phi }_2=\arcsin [\frac{\sqrt{V_{\mathrm{out}}/2{\mathrm{KR}}_L}}{A_1}]& \left(14\right)\end{array}$

When the phase is detected, the differential signal carrying the phase information sent to the transistors Q1 and Q2 are converted into currents i_1ph, i_2ph. At the same time, Q7 and Q8 work at the same DC operating bias as Q1 and Q2. Therefore, the difference between the output current I₁ of Q1 and Q2 and the output current I₂ of Q7 and Q8 is calculated to obtain the current ΔI containing only the phase information, and finally it becomes voltage information V_out through the load resistor R2. A function corresponding to the difference between the phase and the output voltage is obtained, that is, the formula (14). We can obtain from formula (14):

$\begin{array}{cc}\sin \left({\phi }_1-{\phi }_2\right)=\frac{1}{A_1\sqrt{2{\mathrm{KR}}_2}}\sqrt{V_{\mathrm{out}}}& \left(15\right)\end{array}$

• • sin (φ₁-φ₂) is linearly related to √{square root over (V_out)}.

For the amplitude information, the specific derivation is as follows:

Assuming that the signal of the phased array transmitting channel 1 passing through the coupler is v₁=A₁ cos (ωt+φ₁); the signal of the phased array transmitting channel 2 passing through the coupler is v₂=A₂ cos(ωt+φ₁); the difference between the two signals through the transformer is calculated and becomes a differential signal,

$\begin{array}{cc}\Delta V_{+}=\left(A_1-A_2\right)\cos \left(\omega t+{\phi }_1\right)& \left(16\right)\end{array}$ $\begin{array}{cc}\Delta V_{-}=-\left(A_1-A_2\right)\cos \left(\omega t+{\phi }_1\right)& \left(17\right)\end{array}$ $\begin{array}{cc}{i}_{1\mathrm{amp}}={K\left(\Delta V_{+}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(18\right)\end{array}$ $\begin{array}{cc}{i}_{2\mathrm{amp}}={K\left(\Delta V_{-}+v_{\mathrm{gs}}-v_{\mathrm{th}}\right)}^2& \left(19\right)\end{array}$ $K=\frac{W}{2L}\mu C_{\mathrm{ox}}$ $\begin{array}{cc}{I}_1=i_{1\mathrm{amp}}+i_{2\mathrm{amp}}& \left(20\right)\end{array}$ $\begin{array}{cc}{I}_2=2\times i_{\mathrm{dc}}& \left(21\right)\end{array}$ $\begin{array}{cc}\Delta I=I_1-I_2=2K\Delta V_{+}^2={K\left(A_1-A_2\right)}^2+K\cos \left(2\left(\omega t+{\phi }_1\right)\right)& \left(22\right)\end{array}$ $\begin{array}{cc}\mathrm{DC}❘\Delta I❘={K\left(A_1-A_2\right)}^2& \left(23\right)\end{array}$ $\begin{array}{cc}{V}_{\mathrm{out}}=\mathrm{DC}❘\Delta I❘\times R_2={K\left(A_1-A_2\right)}^2{R}_2& \left(24\right)\end{array}$ $\begin{array}{cc}{A}_1-A_2=\sqrt{\frac{V_{\mathrm{out}}}{K{R}_2}}& \left(25\right)\end{array}$

When the amplitude is detected, the differential signal carrying the amplitude information sent to the transistors Q3 and Q4 are converted into currents i_1amp, i_2amp. At the same time, Q5 and Q6 work at the same DC operating bias as Q3 and Q4; therefore, the difference between the output current I₁ of Q3 and Q4 and the output current I₂ of Q5 and Q6 is calculated to obtain the current I₂ that only contains the amplitude information, and finally it becomes the voltage information V_out through the load resistance R2; a function corresponding to the difference between the amplitude and the output voltage is obtained, that is, formula (25); When detecting the amplitude, the amplitude control unit of the phased array transmitting channel 2 is configured to the minimum gain state; at this time, the signal coupled to the power detector by the phased array transmitting channel 2 through the coupler is very small compared with the signal coupled to the power detector by the phased array transmitting channel 1, so A₂ is ignored, which is obtained from formula (25):

$\begin{array}{cc}{A}_1=\sqrt{\frac{V_{\mathrm{out}}}{{\mathrm{KR}}_2}}& \left(26\right)\end{array}$

Then, the voltage amplitude A₁ is converted to power P₁/dBm:

$\begin{array}{cc}{P}_1=10\log \left(V_{\mathrm{out}}\right)-10\log \left({\mathrm{KR}}_2\right)& \left(27\right)\end{array}$

It can be seen from formula (27) that the power P₁ is proportional to 10 log(V_out).

It can be seen from the simulation software verification that the circuit architecture is in good agreement with the theoretical formula channel.

The specific results are shown in FIG. 5.

It can be clearly seen from FIG. 5 that √{square root over (V_out)} is linearly related to sin(φ₁-φ₂), which is consistent with the theoretical derivation, indicating that the self-test circuit can more accurately detect the phase difference between the channels of the phased array system.

As shown in FIG. 6, 10 log(V_out) is proportional to Pa which is consistent with the theoretical derivation, indicating that in the range of the output power (−3 dBm-13 dBm) of the phased array system channel, the self-test link can more accurately detect the amplitude of the phased array system.

In order to ensure that the phased array system can be used normally in a complex electromagnetic-thermal environment, the phased array system needs to resist PVT. As the core module in the phased array system, the performance of the amplitude and phase control module has a crucial impact on the core indicators such as beam biasing, beam scanning, and sidelobe suppression of the phased array. However, when affected by PVT, the precision and accuracy of phase and amplitude control tend to deteriorate more seriously. The current mainstream research on this problem is mainly to design an amplitude and phase control circuit that is less affected by PVT to minimize the impact of PVT on the phased array system, or introduce a compensation circuit to compensate for the amplitude and phase control accuracy deterioration caused by different working environments. However, this method cannot effectively avoid the influence of PVT on the amplitude and phase control of the phased array system. In this context, a test link for the amplitude and phase of the phased array system is proposed, which can be used to quickly and easily detect the amplitude and phase performance of the phased array system after the deterioration of the amplitude and phase performance, thus laying the foundation for the self-calibration of the phased array system.

While the present invention has been described in details with respect to the above preferred embodiments, it should be understood that the above description should not be taken as a limitation of the present invention. Various modifications and alternatives to the present invention will occur to those skilled in the art upon reading the foregoing description. Accordingly, the scope of protection of the present invention should be defined by the appended claims.

Claims

1-4. (canceled)

5. A self-test circuit based on power detector, characterized in that it comprises a power detector, a coupler, a phased array transmitting channel 1 and a phased array transmitting channel 2; Among them, the amplitude and phase information of phased array transmit channels 1 and 2 are extracted from the coupler and input into the self-testing circuit, the power detector, comprised mainly of Q1-Q9 NMOS transistors, detects the amplitude and phase information, outputting a detection voltage;In this circuit, Q1-Q9 form the core components of the power detector, Specifically, Q1, Q2, Q3, and Q4 have their drains connected to node A with their sources linked to the drain of Q9, the gate of Q1 is connected to the positive end of the RF differential signal through a DC blocking capacitor while that of Q2 is linked to its negative end via another DC blocking capacitor, Similarly, for Q3 and Q4 gates are connected to positive and negative ends respectively using similar capacitors, Additionally, gates for transistors from both sets (Q1-Q4 &Q5-Q8) connect either directly or indirectly to bias circuits; their drains link together before connecting to node B while their sources connect back to drain of transistor 9 which in turn connects back through biasing circuits completing a loop connection with source terminals grounded;Transistor 9 serves as a tail current source biased at 600 mV, the capacitance value for all DC blocking capacitors is set at 1 pF whereas parallel load resistors along with filtering capacitors connect each supply terminal separately with nodes A & B respectively; these filtering capacitors hold capacitance values set at 968 fF each while load resistor values remain constant at 1 kΩ;The power detector is divided into two working modes of phase test and amplitude test:When the working mode is the phase test mode:The transistors Q3, Q4, Q5 and Q6 are in the cut-off state by biasing Vbias_amp=0V, and the transistors Q1, Q2, Q7, Q8 and Q9 are in the normal working state by biasing Vbias phase=400 mV; at this time, the transistors Q1, Q2 and transistors Q7, Q8 work at the same DC bias, the four transistors are all biased at Vbias_phase, and the differential signals carrying the phase information are V+_phase and V−_phase; its voltage signals are converted to current signals through the transistors Q1 and Q2 and are carried by i1ph and i2ph, while V+_amp and V−_amp have no signal at this time; at the same time, under the same bias of Q7 and Q8, the corresponding DC current is idc, and at node A, the sum of i1ph and i2ph is I1, and high-frequency signals are filtered out by the capacitor filter; the current signals are converted into voltage signals through load resistor, and the voltages at node A and node B are subtracted to obtain the DC voltage representing the phase information;When the operating mode is amplitude detection mode, the transistors Q1, Q2, Q7, and Q8 are biased at Vbias_phase=0V, and the transistors do not work; the transistors Q3, Q4, Q5, and Q6 are biased at Vbias_amp=400 mV, and the transistors work normally; at this time, the differential signals V+_amp and V−_amp carrying carry amplitude information, the voltage signal after passing through transistors Q3 and Q4 is converted into a current signal, and then transmitted by currents i1amp and i2amp,While V+_phase and V−_phase have no signals; the transistors Q5 and Q6 only have DC bias, and the current generated by the bias is idc; at node A, the sum of i1amp and i2amp is I1, the high-frequency signals are filtered out by the capacitor filter, and the DC current idc corresponding to the transistors Q5 and Q6 is summed to be I2; the currents I1 and I2 are converted to DC voltage through the resistor load, and are subtracted to obtain the DC voltage carrying the amplitude information;When the power detector operates in phase detection mode, the signal of the phased array transmitting channel 1 passing through the coupler is v1=A1 cos(ωt+φ1); and the signal from the phased array transmitter channel 2 through the coupler is v2=A2 cos(ωt+φ2); In this case, the values of A1 and A2 are equal, and the two signals are transformed by a transformer to become a differential signal:

6. A self-test circuit based on power detector according to claim 5, characterized in that, in the phased array transmitting channel 1 and the phased array transmitting channel 2, the variable gain amplifier controls the radio frequency signal by changing the gain; the phase shifter is to change the phase of the radio frequency signal within a 360° range, and the power amplifier is to provide gain and amplify the power of the radio frequency signal to increase the transmitting power of the antenna; the amplitude and phase information of the phased array transmitting channel 1 and the phased array transmitting channel 2 is extracted to the self-test circuit through the coupler, and the power detector detects the amplitude and phase information and outputs the test voltage.