1. Field of the Invention
The present invention relates to a semiconductor circuit arrangement having a circuit element which is formed in an integrated manner in a semiconductor substrate of a first conductivity type and has at least one control terminal and a first and second electrode terminal, the first electrode terminal being formed by a terminal well—embedded within the semiconductor substrate—of a second conductivity type opposite to the first conductivity type and a sub-well region of the second conductivity type which is situated within the terminal well but is doped more highly than the terminal well, and also to a method for producing such a semiconductor circuit arrangement
2. Description of the Related Art
Known examples of such semiconductor circuit arrangements are MOS tetrodes and MOS pentodes having a plurality of control terminals, in particular having at least two gate terminals, namely a high-frequency gate and at least one control gate, which are fabricated either as individual components or in highly integrated form on a semiconductor substrate by means of VLSI technology steps (VLSI=very large scale integration). A suitability for supply voltages of 12 V or more is demanded in particular when such MOS tetrodes are used in automotive engineering. The modern CMOS process fabrication methods are generally only designed for the fabrication of semiconductor circuits for supply voltages of <5 V and are not readily suitable for the fabrication of semiconductor circuits with higher supply voltage ranges. Essential technological reasons for this reside, inter alia, in the excessively small gate oxide thickness and also in an excessively low drain-well breakdown voltage in the semiconductor circuits which are fabricated in modern standard CMOS processes and are therefore not readily suitable for the fabrication of MOS tetrodes and MOS pentodes with supply voltages of 12 V or more.
The present invention is based on the object of providing a semiconductor circuit arrangement, in particular one with a plurality of control terminals, namely at least two gate terminals, one of which is a high-frequency gate, as in the case of tetrodes or pentodes, which has a first electrode terminal which enables supply voltages of 12 V or more, and of specifying a method for producing such a semiconductor circuit arrangement which can be carried out in a simple manner.
The object is achieved by the method for producing a semiconductor circuit arrangement having a circuit element which is formed in an integrated manner in a semiconductor substrate of a first conductivity type and has at least one control terminal and a first and second electrode terminal, the first electrode terminal being formed by a terminal well—embedded within the semiconductor substrate—of a second conductivity type opposite to the first conductivity type and a sub-well region of the second conductivity type which is situated within the terminal well but is doped more highly than the terminal well, the sub-well region of the second conductivity type which is formed in the main surface of the semiconductor substrate and is assigned to the first electrode terminal ends before the well region of the first conductivity type of the at least one control terminal. The object is also achieved by a semiconductor circuit arrangement having a circuit element which is formed in an integrated manner in a semiconductor substrate of a first conductivity type and has at least one control terminal and a first and second electrode terminal, the first electrode terminal being formed by a terminal well—embedded within the semiconductor substrate—of a second conductivity type opposite to the first conductivity type and a sub-well region of the second conductivity type which is situated within the terminal well but is doped more highly than the terminal well, the sub-well region of the second conductivity type which is formed in the main surface of the semiconductor substrate and is assigned to the first electrode terminal ends before the well region of the first conductivity type of the at least one control terminal.
According to the invention, it is provided that the sub-well region of the second conductivity type which is formed in the main surface of the semiconductor substrate and is assigned to the first electrode terminal ends before the well region of the first conductivity type of the at least one control terminal.
Further features, advantages and expediencies of the invention emerge from the following description of exemplary embodiments of the invention with reference to the drawings.
The preferred embodiments described hereinbelow do not limit the scope of the claims.
The semiconductor circuit arrangement shown in
The method thus is further characterized in that the semiconductor circuit arrangement is formed as a discrete component with at least two control terminals. The method of one example provides that the semiconductor circuit arrangement constitutes a high-frequency transistor with at least two control terminals.
In the semiconductor circuit arrangement of a preferred embodiment, the semiconductor circuit arrangement is formed as a discrete component with at least two control terminals. In one embodiment, the semiconductor circuit arrangement constitutes a high-frequency transistor with at least two control terminals.
Although other modifications and changes may be suggested by those skilled in the art, it is the intention of the inventors to embody within the patent warranted hereon all changes and modifications as reasonably and properly come within the scope of their contribution to the art.
Number | Date | Country | Kind |
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199 57 532 | Nov 1999 | DE | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCTEP00/12051 | 11/30/2000 | WO | 00 | 8/21/2002 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO0141187 | 6/7/2001 | WO | A |
Number | Name | Date | Kind |
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5319236 | Fujihira | Jun 1994 | A |
5378913 | Hoeltge | Jan 1995 | A |
5751033 | Miya | May 1998 | A |
5773860 | Kijima et al. | Jun 1998 | A |
5874768 | Yamaguchi et al. | Feb 1999 | A |
6034388 | Brown et al. | Mar 2000 | A |
6320234 | Karasawa et al. | Nov 2001 | B1 |
6646311 | Chatterjee | Nov 2003 | B2 |
Number | Date | Country | |
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20030122212 A1 | Jul 2003 | US |