Semiconductor circuit device and design method therefor

Abstract

In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are diagrams schematically illustrating a step of performing ion implantation using a resist as a mask when a transistor is fabricated.

FIG. 2 is a diagram illustrating a change in transistor characteristics when a value of SP01+SP02 is changed in a CMOS transistor of FIG. 11.

FIG. 3 is a plan view schematically illustrating a cell layout of a semiconductor circuit device according to a first embodiment of the present invention.

FIG. 4 is a plan view schematically illustrating a cell layout of a semiconductor circuit device of the first embodiment, in which two CMOS transistors are provided.

FIGS. 5A to 5E are diagrams for describing a method of arranging cells in an array in a semiconductor circuit device.

FIG. 6 is a plan view schematically illustrating a cell array layout of a semiconductor circuit device according to a second embodiment of the present invention.

FIG. 7 is a plan view schematically illustrating another cell array layout of the semiconductor circuit device of the second embodiment.

FIG. 8 is a plan view illustrating a mask layout for the cell array of the second embodiment of FIG. 6.

FIG. 9 is a plan view schematically illustrating a variation of the cell array layout of the semiconductor circuit device of the second embodiment.

FIG. 10 is a diagram schematically illustrating a structure of a transistor for describing a conventional transistor model.

FIG. 11 is a plan view schematically illustrating an exemplary layout of a conventional cell provided in a portion of a semiconductor substrate.

FIG. 12 is a plan view illustrating a semiconductor circuit device in which cells designed by a conventional method are arranged in an array.

FIG. 13 is a plan view illustrating a mask layout for the conventional cell array of FIG. 12.

Claims

1. A semiconductor circuit device in which a plurality of cells are arranged in an array in a cell array formation region, each cell having a first conductivity type MIS transistor and a second conductivity type MIS transistor, wherein in the cell array formation region, a plurality of first conductivity type first wells and a plurality of second conductivity type second wells are alternately arranged in a gate width direction, andof the first wells and the second wells, a distance between an outer end portion of an outermost well in the gate width direction in the cell array formation region, and an active region formed in the outermost well, is set to be larger than or equal to a predetermined value.

2. The semiconductor circuit device of claim 1, wherein the predetermined value is 1 μm.

3. The semiconductor circuit device of claim 1, wherein an outermost well contact region is provided between the active region and the outer end portion of the outermost well, anda distance from a boundary line between the outermost well and another well adjacent thereto, to the outer end portion of the outermost well, is one time or more and two times or less larger than a distance from the boundary line to a center line of the outermost well contact region.

4. The semiconductor circuit device of claim 1, wherein in a first well located further inside than the outermost well in the gate width direction in the cell array formation region, a first active region and a second active region opposed to each other in the gate width direction are provided, and a first well contact region is provided between the first active region and the second active region, anda distance from a boundary line between the first well and the second well to an end portion in the gate width direction of the first well, is one time or more and two times or less larger than a distance from the boundary line to a center line of the first well contact region.

5. The semiconductor circuit device of claim 3, wherein a distance from an end portion in the gate length direction of an outer frame of the cell to the active region is larger than a distance from the boundary line to the active region.

6. The semiconductor circuit device of claim 3, wherein a distance from an end portion in the gate length direction of an outer frame of the cell to the active region is 1 μm.

7. The semiconductor circuit device of claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type.

8. A semiconductor circuit device in which a plurality of cells are arranged in an array, each cell having an N well and a P well formed in a substrate, a first PMIS active region formed in the N well, a first P-channel type transistor formed on the first PMIS active region and having a gate electrode, a first NMIS active region formed in the P well, a first N-channel type transistor formed on the first NMIS active region and having a gate electrode, a contact N-type region formed in the N well, and a contact P-type region formed in the P well, wherein a distance from a boundary line between the N well and the P well to an end portion in a gate width direction of the N well, is one time or more and two times or less larger than a distance from the boundary line to a center line of the contact N-type region, anda distance from the boundary line to an end portion in the gate width direction of the P well is one time or more and two times or less larger than a distance from the boundary line to a center line of the contact P-type region.

9. A method for designing a semiconductor circuit device in which a plurality of cells are arranged in an array in a cell array formation region, a plurality of first conductivity type first wells and a plurality of second conductivity type second wells being alternately arranged in a gate width direction in the cell array formation region, and each cell having a first conductivity type MIS transistor and a second conductivity type MIS transistor, wherein of the first wells and the second wells, a distance between an outer end portion of an outermost well in the gate width direction in the cell array formation region, and an active region formed in the outermost well, is set to be larger than or equal to a predetermined value, andthe method comprises the steps of: (a) preparing the cells; and(b) arranging the cells in an array in the cell array formation region.

10. A method for designing a semiconductor circuit device, comprising the steps of: (a) preparing cells each having an N well and a P well formed in a substrate, a PMIS active region formed in the N well, a P-type transistor formed on the PMIS active region and having a gate electrode, an NMIS active region formed in the P well, and an N-type transistor formed on the NMIS active region and having a gate electrode;(b) fabricating a cell array by arranging the cells in an array; and(c) adding a dummy region to a cell located at an end portion in a gate width direction of the cell array fabricated in step (b).