The invention relates to a semiconductor component by means of which large currents can be conducted with low resistance in the case of a small surface. The invention relates in addition to a method for producing a semiconductor component, a semiconductor component according to the invention preferably being produced.
Within the electrodes 1 and 2 and also in the substrate 4, an electrical resistance is produced. In order to reduce this resistance, the electrodes 1 and 2, according to the state of the art, are divided over their entire width into a plurality of narrower individual components (1a, 1b, 1c, 2a, 2b) which are then connected in parallel via a so-called bus (6, 7). Such an arrangement is shown in
The buses 6 and 7 guide the current which flows through the individual components 2a, 2b or 1a, 1b, 1c together. The current carrying capacity of the buses 6 and 7 must respectively be so great that it corresponds to the sum of the current carrying capacities of the individual components 1a, 1b, 1c or 2a, 2b. The current carrying capacity of the buses 6 and 7 can be increased for example by increasing the width of the buses. However, the buses 6 and 7 therewith increase the surface area of the total component without this surface area contributing to the supply of current. The additional spatial requirement hereby increases therefore with the current strength and the number of individual components to be supplied by the bus. The dotted regions 10a, 10b in
The component can be connected via bonding wires at bonding spots 11 and 12. The bonding spots 11 and 12 must also be designed in the size thereof such that their current carrying capacity corresponds to the current carrying capacity of the buses 6 or 7 contacted by them. In the case of the bonding spot 12, the current carrying capacity thereof must therefore correspond to the sum of the current carrying capacities of the buses 6 and 6a. However, increasing the bonding spots likewise increases the spatial requirement on the semiconductor disc, which is associated with increased costs. In turn, the spatial requirement increases in addition with the current which is intended to be conductable through the component to be connected.
A further problem in the arrangement shown in
It is therefore the object of the present invention to indicate a semiconductor component, the surface area of which required for contacting is less than in the state of the art, which has in addition smaller series resistances and is furthermore less susceptible to destruction as a result of electrical breakdowns. In addition, it is the object of the invention to indicate a method for producing a semiconductor component with which the mentioned advantages can be achieved.
These objects are achieved by the semiconductor component according to claim and the method for producing a contact according to claim 19. Advantageous developments of the semiconductor component according to the invention and of the method according to the invention are provided by the respective dependent claims.
A semiconductor component according to the invention has a substrate on which at least one oblong first electrode and at least one, preferably oblong, second electrode are disposed. Further correspondingly disposed electrodes with further polarities are possible. The substrate is preferably a conductive layer or a semiconductor layer.
At least one, preferably all of the electrodes, have an oblong form. This means that they extend along a line and, in one or two directions perpendicular to this line, have an essentially constant or only slightly varying extension over the length of the line. According to the invention, the electrodes are now closed in the longitudinal direction thereof, this means that the mentioned line, along which the electrodes extend, is a closed line for each electrode. Closed hereby means that the line or the electrodes merge into each other along their longitudinal direction, i.e. have no beginning and no end. The electrodes are therefore configured such that their surfaces surround a free region not covered by the corresponding electrode.
The electrodes can be closed respectively in the mentioned manner annularly, circularly, elliptically, rectangularly, squarely, triangularly, polygonally or in another manner. The electrode then hereby extends along the edges of the corresponding shape.
The electrodes are preferably disposed in their longitudinal direction parallel to the substrate and parallel to each other. A voltage can preferably be applied between the electrodes such that the at least one first electrode has a first polarity or pole and the at least second electrode has a second polarity or pole and/or such that the electrodes have at least two different functions in the semiconductor component. Parallelism implies here that the shortest spacing of the objects parallel to each other is constant and/or is the same on the total extension or length. There is understood here as polarity or pole preferably the sign of the potential on the corresponding electrode or also the relative potential of the electrodes to each other. Two electrodes, the potential of which has the same sign but different values, have therefore different polarities in this sense. The term function is used here analogously. There is understood by function also the function of the corresponding electrode in the component. If for example the component is a transistor, then the functions of the electrodes can be for example drain, source and gate or emitter, collector and base. In the case of a diode, the polarity or function for example for the one electrode can be the positive pole and, for the other, the negative pole. The same applies for other components.
The electrodes can be configured inter alia to form a semiconductor which is non-blocking as ohmic contact or blocking as Schottky contact.
It is preferred if the electrodes are disposed in a common plane. It is also preferred if the substrate is essentially extended in a planar manner, preferably in one plane. This means that two surfaces of the substrate situated one opposite the other are significantly larger than the other surfaces of the substrate. The electrodes then extend preferably in one or more planes which are situated parallel to those planes in which the substrate extends in a planar manner.
It is preferred that the electrodes are disposed concentrically about common points, such as for example a common centre.
It is possible due to the closed arrangement of the electrodes according to the invention to contact these at any point and thereby to half the undesired series resistance within the electrode relative to an unclosed arrangement. The resistance is halved in that, from each point of the electrode to a contacting externally, for example via a bus, there are two paths along the electrode which are connected to each other in parallel. The conductances of the two paths are added therefore to form a common conductance which is greater than the conductance of the individual paths. The conductance hereby is the inverse resistance.
Preferably, several or all of the first electrodes are now connected by a common bus and/or several or all of the second electrodes are connected by a common bus. Possible further electrodes with further polarities can be connected analogously by further buses.
Preferably, at least one of the buses is disposed in a plane which is parallel to that plane in which the substrate is extended in a planar manner and in which neither the substrate nor the electrodes are disposed. For particular preference, at least one of the buses, preferably all of the buses, is disposed on a side of the electrode orientated away from the substrate. In this case, firstly the electrodes can therefore be disposed on the substrate in a common plane and then, above the electrodes, the bus or buses.
Advantageously, the bus or buses are not disposed directly on the electrodes but at a spacing from the latter. At least one insulating layer is hereby disposed preferably between the buses and the electrodes. It is then preferred if at least one via contact is disposed between at least one of the buses and the electrodes connected by the corresponding bus, via which via contact the electrodes are connected electrically to the bus contacting them. The via contact therefore extends across the spacing between the electrodes and the buses.
The via contacts can extend in particular through holes in the insulating layer. Such holes or openings can be filled for this purpose with a conductive material, such as e.g. metal.
The insulating layer can have or comprise a dielectric and/or polymers.
The via contacts can be configured in the most varied of ways. They can be oblong and they can have inter alia a cuboid or cylindrical shape.
For specific applications, the structure of the insulating layers and via contacts can also be more complicated.
An insulating layer can firstly be applied for example on the electrodes, said layer having openings above the electrodes. One or more metal layers can be applied on this insulating layer which extends also into the openings and contacts the electrodes through them. A separate metal layer or a separate region of the metal layer can be provided here for each polarity.
For more than two polarities, at least one further insulating layer and also at least one further metal layer which has separate regions for different polarities can be applied correspondingly on the metal layers at least in regions, corresponding to what was described above for the other layers.
If electrodes of several poles or polarities are connected respectively via several buses, then the buses can be disposed in different planes or in a common plane. Since the electrodes are extended longitudinally, it is possible to dispose a plurality of buses such that all the electrodes extend in portions below each bus, the via contacts however being disposed only between a given bus and the electrodes contacted by said bus. The other electrodes extend without electrical contact to this bus along between the substrate and the bus. Preferably, at least one insulating layer is disposed between the electrodes and those buses which do not contact these electrodes.
It is possible, in particular in the above-mentioned constellation, that the buses are extended in a planar manner in the plane of their arrangement. They can hereby extend in a planar manner over a part of the surface area of the substrate. It is thereby advantageous to make the surface area of the buses as large as possible. It is therefore preferred if the buses together cover the surface of the substrate in large parts, preferably essentially completely.
It is particularly preferred to use the surface area of one or more supply buses as a bonding spot which serves to connect the semiconductor component via bonding wires. As a result, the contacting can be effected by means of bonding wires without additional semiconductor surface area being required for this purpose.
As a result of the described contacting of the electrodes by means of buses which are disposed vertically above the semiconductor component and the electrodes, the active surface can be used doubled by the active component. The supply bus therefore requires no additional semiconductor disc surface area.
Preferably, the via contacts extend longitudinally parallel to those electrodes which are connected by them to a bus. The via contacts can hereby extend along the electrodes in that region in which the electrodes extend below the buses contacting them.
The semiconductor component preferably has at least one transistor and/or one diode or is a transistor or a diode. Such a transistor is preferably a field effect transistor.
There are possible inter alia as semiconductor materials preferably those which contain or comprise at least one nitride of a main group III element. These materials are therefore inter alia GaN, AlN, InN, GaAlN, GaInN, AlInN and AlInGaN. Those can be particularly resistant to high temperatures, preferably greater than or equal to 100° C., particularly preferred greater than or equal to 300° C., particularly preferred greater than or equal to 500° C., particularly preferred greater than or equal to 700° C.
The invention is intended to be explained subsequently with reference to a few Figures, by way of example. The features shown in the Figures can be produced respectively also individually in the invention.
There are shown
The buses 6 and 7 are not disposed directly on the electrodes 1a, 1b, 1c and 2a, 2b. Rather an insulating layer 43 is disposed between the electrodes and the buses 6 and 7. The electrical connection between the electrodes 2a and 2b to the bus 7 is hereby achieved by the via contacts 42a or 42b penetrating the insulating layer 43. Correspondingly, the electrodes 1a, 1b and 1c are contacted with the bus 6 through via contacts 41a, 41b or 41c. The via contacts 41a, 41b, 41c and 42a, 42b can hereby have an oblong configuration in the direction perpendicular to the drawing plane.
The insulating material 43 is disposed respectively between the electrodes 1a, 1b, 1c and the adjacent electrodes 2a, 2b. Furthermore, the insulating material 43 is disposed between the plane of the electrodes 1, 2 and the buses 6, 7 which is penetrated however by the via contacts 41a, 41b, 41c, 42a, 42b.
Number | Date | Country | Kind |
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10 2007 028 458.8 | Jun 2007 | DE | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/EP2008/004839 | 6/16/2008 | WO | 00 | 3/29/2010 |