Semiconductor device and a method of manufacturing the same

Abstract

Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to one embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor device according to the one embodiment of the present invention;

FIG. 3 is an equivalent circuit diagram of a memory cell;

FIG. 4 is a table showing one example of application conditions of a voltage to each site of a selected memory cell at the time of “program”, “erase” and “read”;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor device according to the one embodiment of the present invention during a manufacturing step thereof;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 5;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 6;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 7;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 8;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 9;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 10;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 11;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 12;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 13;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 14;

FIG. 16 is a fragmentary cross-sectional view of a semiconductor device according to Comparative Example;

FIG. 17 is a fragmentary plan view of a semiconductor device according to another embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor device according to the another embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor device according to the another embodiment of the present invention during a manufacturing step thereof;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 19;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 20;

FIG. 22 is a fragmentary cross-sectional view of a semiconductor device according to a further embodiment of the present invention during a manufacturing step thereof;

FIG. 23 is a fragmentary cross-sectional view of a resistive element formation region of the semiconductor device during the same manufacturing step as that of FIG. 22;

FIG. 24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 22;

FIG. 25 is a fragmentary cross-sectional view of a resistive element formation region of the semiconductor device during the same manufacturing step as that of FIG. 24;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 24;

FIG. 27 is a fragmentary cross-sectional view of a resistive element formation region of the semiconductor device during the same manufacturing step as that of FIG. 26;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step thereof following that of FIG. 26; and

FIG. 29 is a fragmentary cross-sectional view of a resistive element formation region of the semiconductor device during the same manufacturing step as that of FIG. 28.

Claims

1. A semiconductor device comprising: a first gate electrode and a second gate electrode which are formed over a semiconductor substrate and are adjacent to each other;a first insulating film formed between the first gate electrode and the semiconductor substrate;and a second insulating film formed between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode and having a charge accumulator portion inside of the second insulating film,wherein a metal silicide film is formed over an upper surface of the first gate electrode but not formed at the end portion and nearby region thereof, on the side of the first gate electrode, of the surface of the second gate electrode not in contact with the second insulating film.

2. A semiconductor device according to claim 1, wherein the metal silicide film is not formed over an upper surface of the second gate electrode.

3. A semiconductor device according to claim 1, wherein the height of the second gate electrode is lower than the height of the first gate electrode.

4. A semiconductor device according to claim 3, wherein a silicon oxide film is formed over an upper portion of the second gate electrode.

5. A semiconductor device according to claim 4, further comprising a silicon nitride film formed over the semiconductor substrate to cover the first and second gate electrodes, wherein the silicon oxide film is formed between the silicon nitride film and the second gate electrode.

6. A semiconductor device according to claim 5, further comprising: an interlayer insulating film formed over the silicon nitride film; anda contact hole formed in the interlayer insulating film and the silicon nitride film,wherein the silicon nitride film functions as an etching stopper film when the contact hole is formed in the interlayer insulating film.

7. A semiconductor device according to claim 4, further comprising a sidewall insulating film formed over side walls, on the sides of the first and second gate electrodes not facing to each other, wherein the sidewall insulating film has the same material as that of the silicon oxide film.

8. A semiconductor device according to claim 7, wherein the silicon oxide film and the sidewall insulating film are formed in the same step.

9. A semiconductor device according to claim 7, further comprising: a first semiconductor region formed in the semiconductor substrate in self alignment with the sidewall of the second gate electrode; anda second semiconductor region formed in the semiconductor substrate in self alignment with the sidewall insulating film formed over the sidewall of the second gate electrode.

10. A semiconductor device according to claim 1, further comprising: an interlayer insulating film formed over the semiconductor substrate to cover the first and second gate electrodes;a first contact hole formed in the interlayer insulating film over the second gate electrode; anda conductor portion formed in the first contact hole and electrically coupled to the second gate electrode,wherein the metal silicide film is formed over a region of the second gate electrode to be coupled with the conductor portion.

11. A semiconductor device according to claim 1, further comprising a nonvolatile memory, wherein the first and second gate electrodes are gate electrodes constituting the nonvolatile memory.

12. A manufacturing method of a semiconductor device, comprising the steps of: (a) forming a first gate electrode over the main surface of a semiconductor substrate via a first insulating film;(b) forming, over the main surface of the semiconductor substrate and sidewall of the first gate electrode, a second insulating film having therein a charge accumulator portion;(c) forming, over the second insulating film, a second gate electrode adjacent to the first gate electrode via the second insulating film; and(d) forming a metal silicide film over an upper surface of the first gate electrode,wherein in the step (c), the second gate electrode is formed with a height smaller than that of the first gate electrode, andwherein in the step (d), the metal silicide film is not formed at the end portion and nearby region on the side of the first gate electrode, of the surface of the second gate electrode not in contact with the second insulating film.

13. A manufacturing method of a semiconductor device according to claim 12, wherein the step (c) comprises the sub-steps of: (c1) forming a first conductor film for the second gate electrode over the main surface of the semiconductor substrate to cover the first gate electrode; and(C2) etching back the first conductor film to leave, over the sidewall of the first gate electrode, the first conductor film via the second insulating film and remove the first conductor film from the other region,wherein in the step (c2), the first conductor film is etched back until the height of the first conductor film remaining over the sidewall of the first gate electrode via the second insulating film becomes lower than that of the first gate electrode.

14. A manufacturing method of a semiconductor device according to claim 12, further comprising, after the step (c) and before the step (d), a step of: (e) forming sidewall insulating films over the upper portion and sidewall of the second gate electrode and sidewall of the first gate electrode, respectively,wherein the step (d) comprises the sub-steps of:(d1) forming a metal film over the main surface of the semiconductor substrate to cover the first and second gate electrodes and the sidewall insulating film; and(d2) reacting the first gate electrode with the metal film to form the metal silicide film over the upper surface of the first gate electrode.

15. A manufacturing method of a semiconductor device according to claim 14, wherein the metal film formed in the step (d1) is in contact with the upper surface of the first gate electrode and the surface of the second gate electrode exposed between the sidewall insulating films formed over the upper portion and the sidewall of the second gate electrode.

16. A manufacturing method of a semiconductor device according to claim 14, wherein the step (e) comprises the sub-steps of: (e1) forming a third insulating film for the formation of the sidewall insulating film over the main surface of the semiconductor substrate to cover the first and second gate electrodes; and(e2) etching back the third insulating film to leave the third insulating film over the upper portion and sidewall of the second gate electrode and the sidewall of the first gate electrode and remove the third insulating film from the other region.

17. A manufacturing method of a semiconductor device according to claim 16, further comprising, after the step (e2) but before the step (d), a the step of: (e3) implanting ions into the semiconductor substrate, while using the sidewall insulating film over the sidewall of the first gate electrode and the sidewall insulating film over the sidewall of the second gate electrode as an ion injection blocking mask.

18. A manufacturing method of a semiconductor device according to claim 17, wherein semiconductor regions for source and drain are formed in the semiconductor substrate by the ion implantation in the step (e3).

19. A manufacturing method of a semiconductor device according to claim 14, further comprising, after the step (e) but before the step (d), the steps of: (f1) forming a fourth insulating film over the main surface of the semiconductor substrate to cover the first and second gate electrodes and the sidewall insulating film, and;(f2) etching the fourth insulating film to leave the fourth insulating film over the upper portion of the second gate electrode locally.

20. A manufacturing method of a semiconductor device according to claim 19, wherein in the step (f2), the fourth insulating film is left locally also in a resistive element formation region of the semiconductor substrate.