This application claims the benefit of the Korean Application No. P2003-0101555 filed on Dec. 31, 2003, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and fabricating method thereof, and more particularly, to a capacitor and a fabricating method thereof, by which capacitance is enhanced by increasing an effective area of a lower electrode of the capacitor.
2. Discussion of the Related Art
Generally, in a unit cell configured with a MOS transistor and a capacitor, device characteristics are considerably affected by capacitance of the capacitor. As a capacitor occupying area is reduced according to a highly increasing degree of semiconductor device integration, large capacitance of a capacitor is badly needed more than ever.
To increase capacitance of a capacitor, there are various methods such as a method of increasing an effective area of a capacitor, a method of thinning a dielectric layer between upper and lower electrodes, a method of forming a dielectric layer of a high dielectric constant, and the like.
Yet, the method of thinning a dielectric layer lowers reliability of a semiconductor device. And, the method of forming a dielectric layer of a high dielectric constant needs to develop a new capacitor fabricating process.
Hence, many efforts are made to develop the method of increasing an effective area.
Referring to
In such a capacitor structure of the related art, since the lower electrode 102 has a planar shape, an area of the lower electrode 102 is decreased according to a reduced design rule of semiconductor device.
Hence, a structural limitation is put on the related art capacitor in maximizing capacitance in a microscopic device.
Accordingly, the present invention is directed to a semiconductor device and fabricating method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and fabricating method thereof, by which capacitance is enhanced by increasing an effective area of a lower electrode of a capacitor.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor device according to the present invention includes a first lower electrode on a semiconductor substrate, a second lower electrode on the first electrode having a type or “wing”-type cross-section, a dielectric layer covering surfaces of the first and second lower electrodes, and an upper electrode on the dielectric layer.
In another aspect of the present invention, a method of fabricating a semiconductor device includes the steps of forming a first lower electrode on a substrate, sequentially stacking a first sacrificial layer, a first metal layer, and a second sacrificial layer on the first lower electrode, forming a trench by etching the second sacrificial layer, the first metal layer, and the first sacrificial layer to expose a central part of the first lower electrode, forming a second metal layer over the substrate including the exposed central part of the first lower electrode and the second sacrificial layer, patterning the second metal layer, the second sacrificial layer, the first metal layer, and the first sacrificial layer, removing the remaining first and second sacrificial layers to expose a second lower electrode, forming a dielectric layer covering surfaces of the first and second lower electrodes, and forming an upper electrode on the dielectric layer.
Preferably, the first and second sacrificial layers comprise an oxide.
Preferably, the first and second sacrificial layers are removed by wet etching.
Preferably, the dielectric layer is formed by chemical vapor deposition.
Preferably, the upper electrode forming step includes the steps of forming a third metal layer over the dielectric layer and patterning the third metal layer and the dielectric layer.
More preferably, the third metal layer is formed by chemical vapor deposition.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Referring to
Specifically, the lower electrode having a shelf shape includes a first lower electrode 203 having a planar shape and a second lower clectrode 210 on the first lower electrode 203. And, the second lower clectrode 210 has a type or wing-type cross-section. The term “wing-type cross section” generally means that the electrode has a plurality of substantially horizontal plates with at least one insulating material interposed between any two adjacent plates, preferably where there is also at least one substantially horizontal plate of an adjacent electrode interposed between two such adjacent plates of the wing-type electrode, insulated from the wing-type electrode plates by the insulating material. The first lower electrode 203 may include an Al layer and a Ti/TiN layer stacked on the Al layer. And, the second lower electrode 210 may comprise a Ti/TiN bilayer.
And, the dielectric layer 211 is formed on a surface of the lower electrode 203 and 210.
Moreover, the upper electrode 212 is formed on a surface of the dielectric layer 211.
Hence, capacitance of the capacitor of the present invention is increased since an effective area of the lower electrode 203 and 210 contacting with the dielectric layer 211 is mostly increased due to the second lower electrode 210.
Referring to
A first metal layer is deposited 1,000˜1,500 Å thick on the insulating interlayer 202. The first metal layer is patterned by photolithography to form a first lower electrode 203. In doing so, the metal layer for forming the first lower electrode 203 preferably comprises Al or Al—Cu alloy. Alternatively, the first lower electrode 203 can be formed of a metal which has a high work function and low reactivity with a dielectric layer 211 formed thereon, such as Pt, Ru, Ir, Rh, Os, and the like. Optionally, a barrier metal layer (not shown in the drawing) can be stacked on the first metal layer comprising Ti or Ti/TiN.
A first sacrificial oxide layer 204, a second metal layer 205, and a second sacrificial oxide layer 206 sequentially stacked over the substrate including the first lower electrode 203. In doing so, the second metal layer 205 can be formed from a single layer of Ti or a double layer of Ti/TiN. In case of forming the double layer as the second metal layer 205, Ti deposition by IMP (ionized metal plasma) or collimator sputtering and TiN deposition by MOCVD (metal organic chemical vapor deposition) are sequentially carried out.
Subsequently, photoresist is coated on the second sacrificial oxide layer 206. Exposure and development are carried out on the photoresist to form a first photoresist pattern 207 exposing a prescribed portion of the second sacrificial oxide layer 206 over a central part of the first lower electrode 203.
Referring to
And, a third metal layer 208 is formed over the substrate 201 including the exposed central part of the first electrode 203 and the second sacrificial oxide layer 206. In doing so, the third metal layer 208 can be formed from a single layer of Ti or a double layer of Ti/TiN.
Referring to
The third metal layer 208, the second sacrificial oxide layer 206, the second metal layer 205, and the first sacrificial oxide layer 204 are etched using the second photoresist pattern 209 as an etch mask to expose at least a portion of the first lower electrode 203. The exposed portion of first lower electrode 203 may be used for subsequent formation of a contact/via thereto, to connect first lower electrode 203 electrically to overlying metallization (not shown).
Referring to type or wing-type cross-section is formed. Thus, the first lower electrode 203 and the second lower electrode 210 configure a lower electrode of a capacitor. In this case, the second lower electrode 210 includes the second metal layer pattern 205a and the third metal layer pattern 208a.
Referring to type or wing-type cross-section to increase an effective area of the lower electrode contacting with the dielectric layer 211.
Subsequently, a fourth metal layer for forming an upper electrode is deposited over the substrate including the dielectric layer 211 by chemical vapor deposition. In doing so, the fourth metal layer can be formed of the same material of the first lower electrode 203.
Finally, the fourth metal layer and the dielectric layer 211 are selectively patterned to remain on a specific area to complete a dielectric layer pattern 211 and an upper electrode 212 of the capacitor.
Accordingly, in the present invention, the lower electrode having the type or wing type cross-section increases the effective area contacting with the dielectric layer, whereby capacitance of the capacitor is maximized.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Number | Date | Country | Kind |
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10-2003-0101555 | Dec 2003 | KR | national |
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Number | Date | Country | |
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20050142732 A1 | Jun 2005 | US |