This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-196706, filed on Sep. 24, 2013; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and imaging device.
There are semiconductor devices that use thin film transistors. There are imaging devices that use thin film transistors. It is desirable to suppress fluctuation of the characteristics in such semiconductor devices and imaging devices.
According to one embodiment, a semiconductor device includes a semiconductor layer, a first gate electrode, a second gate electrode, an insulating film, a first electrode, a second electrode, a third electrode, and a fourth electrode. The semiconductor layer includes a first semiconductor portion and a second semiconductor portion being continuous with the first semiconductor portion. The first semiconductor portion includes a first portion, a second portion separated from the first portion in a first direction, and a third portion provided between the first portion and the second portion. The second semiconductor portion includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion is separated from the first portion in a second direction intersecting the first direction. The fifth portion is separated from the second portion in the second direction. The sixth portion is provided between the fourth portion and the fifth portion. The first gate electrode is provided to be separated from the third portion in a third direction intersecting a plane including the first direction and the second direction. The second gate electrode is provided to be separated from the sixth portion in the third direction and separated from the first gate electrode in the second direction. The insulating film is provided at a first position between the first gate electrode and the semiconductor layer and at a second position between the second gate electrode and the semiconductor layer. The first electrode is provided to be separated from the first gate electrode, separated from the second gate electrode, and electrically connected to the first portion. The second electrode is provided to be separated from the first gate electrode, separated from the second gate electrode, separated from the first electrode, and electrically connected to the second portion. The third electrode is provided to be separated from the first gate electrode, separated from the second gate electrode, separated from the first electrode, separated from the second electrode, and electrically connected to the fourth portion. The fourth electrode is provided to be separated from the first gate electrode, separated from the second gate electrode, separated from the first electrode, separated from the second electrode, separated from the third electrode, and electrically connected to the fifth portion.
Various embodiments will be described hereinafter with reference to the accompanying drawings.
The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. Further, the dimensions and/or the proportions may be illustrated differently between the drawings, even for identical portions.
In the drawings and the specification of the application, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.
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The semiconductor layer 10 includes a first semiconductor portion 12 and a second semiconductor portion 13. The first semiconductor portion 12 includes a first portion 10a, a second portion 10b, and a third portion 10c. The second semiconductor portion 13 includes a fourth portion 10d, a fifth portion 10e, and a sixth portion 10f. The first semiconductor portion 12 and the second semiconductor portion 13 are provided to be continuous.
A first direction from the first portion 10a toward the second portion 10b is taken as an X-axis direction. One direction perpendicular to the X-axis direction is taken as a Z-axis direction. A direction perpendicular to the X-axis direction and the Z-axis direction is taken as a Y-axis direction.
The third portion 10c is provided between the first portion 10a and the second portion 10b. The fourth portion 10d is separated from the first portion 10a in a second direction (e.g., the Y-axis direction) intersecting the X-axis direction. The fifth portion 10e is separated from the second portion 10b in the second direction (e.g., the Y-axis direction) intersecting the X-axis direction. The sixth portion 10f is provided between the fourth portion 10d and the fifth portion 10e.
When projected onto the X-Y plane, the first gate electrode 20a overlaps at least a portion of the third portion 10c. When projected onto the X-Y plane, the second gate electrode 20b overlaps at least a portion of the sixth portion 10f.
The semiconductor layer 10 has a first semiconductor side 10p and a second semiconductor side 10q. The second semiconductor side 10q is separated from the first semiconductor side 10p in the Y-axis direction.
The first gate electrode 20a has a first gate side 23a and a second gate side 23b. The second gate side 23b is provided between the second semiconductor side 10q and the first gate side 23a when projected onto the X-Y plane.
The second gate electrode 20b has a third gate side 23c and a fourth gate side 23d. The fourth gate side 23d is provided between the second semiconductor side 10q and the third gate side 23c when projected onto the X-Y plane.
A first distance L1 is the distance along the Y-axis direction between the first semiconductor side 10p and the first gate side 23a. A second distance L2 is the distance along the Y-axis direction between the second gate side 23b and the third gate side 23c. For example, the first distance L1 is 0.3 μm (micrometers) or more. For example, the second distance L2 is 0.5 μm or more.
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The semiconductor device 110 includes an insulating film 15. The insulating film 15 is provided at a first position between the third portion 10c and the first gate electrode 20a and at a second position between the sixth portion 10f and the second gate electrode 20b. In other words, the insulating film 15 has a first position provided between the third portion 10c and the first gate electrode 20a and a second position provided between the sixth portion 10f and the second gate electrode 20b.
The semiconductor device 110 includes a first electrode 21a, a second electrode 21b, a third electrode 21c, and a fourth electrode 21d.
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The insulating film 15 functions as a gate insulator film in the first transistor 22a and the second transistor 22b.
The first electrode 21a is, for example, a source electrode of the first transistor 22a. The second electrode 21b is, for example, a drain electrode of the first transistor 22a.
The third electrode 21c is, for example, a source electrode of the second transistor 22b. The fourth electrode 21d is, for example, a drain electrode of the second transistor 22b.
The first gate electrode 20a and the second gate electrode 20b include, for example, Cu (copper). The insulating film 15 includes, for example, a silicon nitride film. The insulating film 15 may have a stacked structure. For example, a silicon oxide film or a high-k film may be stacked on the silicon nitride film as the stacked structure. For example, an aluminum oxide film, a tantalum oxide film, a hafnium oxide film, a titanium oxide film, or the like is used as the high-k film.
The semiconductor layer 10 includes, for example, an oxide including oxygen, In (indium), and at least one selected from Ga (gallium) and Zn (zinc). The semiconductor layer 10 includes, for example, an amorphous oxide semiconductor such as In—Ga—Zn—O (hereinbelow, called InGaZnO), etc. InGaZnO is formed as a film by, for example, sputtering. InGaZnO is formed uniformly as a film over a wide surface area at room temperature. Thereby, a thin film transistor can be formed at a relatively low temperature of, for example, about 300° C. to 400° C. A thin film transistor having high reliability and small fluctuation can be formed. The mobility due to the field effect of the carriers of InGaZnO is about 10 times the mobility due to the field effect of the carriers of amorphous silicon. Thereby, good characteristics can be obtained.
The first electrode, the second electrode, the third electrode, and the fourth electrode include, for example, at least one selected from Mo (molybdenum), Ti (titanium), Al (aluminum), ITO (indium tin oxide), IZO (indium zinc oxide), TiN (titanium nitride), TaN (tantalum nitride), and Mo2N (molybdenum nitride).
The semiconductor device 110 includes multiple transistors. The multiple transistors include one semiconductor layer 10 that is provided to be continuous. The multiple transistors share the semiconductor layer 10. The semiconductor device 110 according to the embodiment may include two or more thin film transistors.
The thin film transistors according to the embodiment may be included in, for example, CMOS image sensors. The downscaling of CMOS image sensors is advancing. The light reception surface area of photodiodes is decreasing; and there are cases where the S/N ratio is small. The light reception surface area of the photodiodes is reduced in the case where amplifier transistors and/or reset transistors are provided on Si which is the substrate. The thin film transistors according to the embodiment are provided in the interconnect layer. Thereby, for example, the light reception surface area of the photodiodes can be increased.
In the case where the thin film transistors are provided in the interconnect layer, the process may fluctuate in the pattern formation of the semiconductor layer 10. Thereby, the characteristics of the thin film transistors may fluctuate. In the semiconductor device 110 according to the embodiment, the multiple transistors include one semiconductor layer 10 that is provided to be continuous. The multiple transistors are provided in one semiconductor layer 10 that is provided to be continuous. Thereby, for example, fine pattern formation of the semiconductor layer 10 can be avoided. The fluctuation of the process in the pattern formation of the semiconductor layer 10 can be suppressed. The fluctuation of the characteristics of the thin film transistors can be suppressed. According to the embodiment, a semiconductor device is provided in which the fluctuation of the characteristics is suppressed.
In the semiconductor device 110, InGaZnO is used as the semiconductor layer 10. The thickness of the InGaZnO is, for example, not less than 5 nm and not more than 100 nm. It is favorable for the thickness to be not less than 10 nm and not more than 50 nm. In such a case, the first distance L1 is, for example, 0.3 μm or more.
The distance along the second direction between the first semiconductor side 10p and the first electrode 21a is, for example, 0.24 μm or more and is, for example, 0.8 times the first distance L1 or more. Thereby, for example, the fluctuation of the characteristics of the transistors due to the fluctuation of the resistance of the semiconductor layer 10 can be suppressed.
The second distance L2 is, for example, 0.5 μm or more.
The distance along the second direction (the Y-axis direction) between the first electrode 21a and the third electrode 21c is, for example, 0.4 μm or more, e.g., 0.8 times the second distance L2 or more. Thereby, for example, the effect on the adjacent channel portion in the formation of the source/drain electrodes can be suppressed. The occurrence of the fluctuation of the characteristics of the transistors can be suppressed.
According to the embodiment, a thin film transistor is provided in which the fluctuation is suppressed.
An example of a method for manufacturing the semiconductor device 110 will now be described.
The thin film transistor is provided in, for example, the interconnect layer of a CMOS process.
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After the film formation of the semiconductor layer 10, the semiconductor layer 10 may be patterned by etching. The insulating film 15 functions as an etching stopper in the process of patterning the semiconductor layer 10. When dry etching is used, there are cases where the difference between the etching rate of the semiconductor layer 10 and the etching rate of the insulating film 15 is small. There are cases where the insulating film 15 is etched excessively. Thereby, defects such as leaks, etc., may occur in the thin film transistor. It is desirable for wet etching to be used as the etching. Thereby, for example, excessive etching of the insulating film 15 is suppressed. The semiconductor layer 10 may not be patterned. Thereby, the excessive etching of the insulating film 15 does not occur.
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The film formation of the second inter-layer insulating film 25b is performed at, for example, 200° C. to 300° C. and favorably at 230° C. to 270° C.
Subsequently, heat treatment is performed inside a clean oven or inside a quartz furnace. The temperature of the heat treatment is, for example, 300° C. to 500° C. It is favorable for the temperature to be 350° C. to 450° C. Ambient air or a nitrogen atmosphere is used as the atmosphere of the heat treatment.
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Subsequently, heat treatment is performed inside a clean oven or inside a quartz furnace. The temperature of the heat treatment is, for example, 300° C. to 500° C. It is favorable for the temperature to be 350° C. to 450° C. Ambient air or a nitrogen atmosphere is used as the atmosphere of the heat treatment.
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According to the embodiment, a thin film transistor is provided in which the fluctuation is suppressed.
In the semiconductor device 111, the first gate electrode 20a and the second gate electrode 20b are provided on the semiconductor layer 10. The first gate electrode 20a is provided between the first electrode 21a and the second electrode 21b. The second gate electrode 20b is provided between the third electrode 21c and the fourth electrode 21d. For example, the second inter-layer insulating film 25b that is between the semiconductor layer 10 and the first gate electrode 20a functions as a gate insulator film. Otherwise, the configuration, the material, etc., are similar to those of the semiconductor device 110 according to the first embodiment.
The semiconductor device 112 includes a first conductive unit 30a and a second conductive unit 30b. The first conductive unit 30a is provided on the first gate electrode 20a. The first conductive unit 30a is provided between the first electrode 21a and the second electrode 21b. The second conductive unit 30b is provided on the second gate electrode 20b. The second conductive unit 30b is provided between the third electrode 21c and the fourth electrode 21d. Otherwise, the configuration, the material, etc., are similar to those of the semiconductor device 110 according to the first embodiment.
The multiple thin film transistors that are provided in the semiconductor device 111 and the semiconductor device 112 include one semiconductor layer 10 that is provided to be continuous. According to the embodiment, a semiconductor device is provided in which the fluctuation of the characteristics is suppressed.
The imaging device 200 according to the third embodiment is a CMOS image sensor using a CMOS process.
The first transistor 19a includes a first electrode 18a and a second electrode 18b. The second transistor 19b includes a third electrode 18c and a fourth electrode 18d.
The imaging device 200 includes a first pixel unit 80a and a second pixel unit 80b. For example, the first pixel unit 80a and the second pixel unit 80b are adjacent pixel units when projected onto the X-Y plane. The first pixel unit 80a includes the first photodiode 70a, the first transfer transistor 81a, and a first interconnect 82a. The second pixel unit 80b includes the second photodiode 70b, the second transfer transistor 81b, and a second interconnect 82b.
The first transfer transistor 81a is provided on the first photodiode 70a. The first photodiode 70a is electrically connected to the first interconnect 82a via the first transfer transistor 81a. The first interconnect 82a is electrically connected to the first transistor 19a. The first interconnect 82a is electrically connected to the first electrode 18a or the second electrode 18b.
The second transfer transistor 81b is provided on the second photodiode 70b. The second photodiode 70b is electrically connected to the second interconnect 82b via the second transfer transistor 81b. The second interconnect 82b is electrically connected to the second transistor 19b. The second interconnect 82b is electrically connected to the third electrode 18c or the fourth electrode 18d.
The first transistor 19a processes the signal of the first pixel unit 80a. The first transistor 19a is, for example, an amplifier transistor of the first pixel unit 80a or a reset transistor of the first pixel unit 80a. The second transistor 19b processes the signal of the second pixel unit 80b. The second transistor 19b is, for example, an amplifier transistor of the second pixel unit 80b or a reset transistor of the second pixel unit 80b.
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In the imaging device 200 according to the embodiment, the thin film transistors are provided in the interconnect layer. Thereby, for example, the light reception surface area of the photodiodes can be increased. The multiple thin film transistors include one semiconductor layer 10 that is provided to be continuous. Thereby, the fluctuation of the thin film transistors can be suppressed. According to the embodiment, an imaging element is provided in which the fluctuation of the characteristics is suppressed.
According to the embodiments, a semiconductor device and an imaging device are provided in which the fluctuation of the characteristics is suppressed.
In the specification of the application, “perpendicular” and “parallel” refer to not only strictly perpendicular and strictly parallel but also include, for example, the fluctuation due to manufacturing processes, etc. It is sufficient to be substantially perpendicular and substantially parallel.
Hereinabove, embodiments of the invention are described with reference to specific examples. However, the invention is not limited to these specific examples. For example, one skilled in the art may similarly practice the invention by appropriately selecting specific configurations of components such as the semiconductor layer, the gate electrode, the insulating film, the electrode, etc., from known art; and such practice is within the scope of the invention to the extent that similar effects can be obtained.
Further, any two or more components of the specific examples may be combined within the extent of technical feasibility and are included in the scope of the invention to the extent that the purport of the invention is included.
Various other variations and modifications can be conceived by those skilled in the art within the spirit of the invention, and it is understood that such variations and modifications are also encompassed within the scope of the invention.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
Number | Date | Country | Kind |
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2013-196706 | Sep 2013 | JP | national |