BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross sectional view showing the steps of a semiconductor device manufacturing method of the first embodiment of the present invention;
FIG. 2 is a flowchart showing the steps of the semiconductor device manufacturing method of the first embodiment;
FIG. 3 illustrates a design pattern of a reinforcement or supporting member;
FIG. 4 is a schematic cross sectional view showing regions to be thinned of the supporting member;
FIG. 5 illustrates schematic views of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 3, manufactured by the semiconductor device manufacturing method of the first embodiment;
FIG. 6 illustrates another design pattern of the supporting member;
FIG. 7 illustrates schematic views of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 6, manufactured by the semiconductor device manufacturing method of the first embodiment;
FIG. 8 illustrates a further design pattern of the supporting member;
FIG. 9 illustrates schematic views of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 8, manufactured by the semiconductor device manufacturing method of the first embodiment;
FIG. 10 illustrates a still further design pattern of the supporting member;
FIG. 11 illustrates schematic views of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 10, manufactured by the semiconductor device manufacturing method of the first embodiment;
FIG. 12 illustrates still further design patterns of the supporting member;
FIG. 13 illustrates schematic views of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 12, manufactured by the semiconductor device manufacturing method of the first embodiment;
FIG. 14 is a schematic cross sectional view showing the steps of a semiconductor device manufacturing method of the second embodiment of the present invention;
FIG. 15 is a flowchart showing the steps of the semiconductor device manufacturing method of the second embodiment;
FIG. 16 is a schematic cross sectional view showing the steps of a semiconductor device manufacturing method of the third embodiment of the present invention;
FIG. 17 is a flowchart showing the steps of the semiconductor device manufacturing method of the third embodiment;
FIG. 18 illustrates a design pattern of the supporting member in the semiconductor device manufacturing method of the third embodiment; and
FIG. 19 is a schematic view of an integrated circuit chip with the supporting member of the pattern, shown in FIG. 18, manufactured by the semiconductor device manufacturing method of the third embodiment.
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor device and a method of manufacturing the same (referred to as an “inventive method” hereinafter) according to the present invention will be described in the form of embodiments, referring to the relevant drawings.
First Embodiment
The first embodiment of the present invention (referred to as “this embodiment” for ease of the description) will now be described referring to FIGS. 1 to 13. FIG. 1 is a schematic cross sectional view of steps, FIG. 1A to FIG. 1E, for manufacturing a semiconductor device of this embodiment. FIG. 2 is a flowchart showing the steps of FIG. 1 and the following description will be made using the steps numbered in FIG. 2.
The schematic cross sectional view of FIG. 1 as well as the other schematic cross sectional views for explaining the second and third embodiments are simply illustrative but not scaled nor sized to actual measurements.
As shown in FIG. 1A, the flowchart starts with providing two or more integrated circuits 11 on the primary side of a semiconductor substrate 10 made of a silicon material or the like (Step #1). Then, the semiconductor substrate 10 is thinned by, for example, polishing its back side (not shown). It is desirable in the step of thinning to protect the primary side of the integrated circuit 10 with protective tapes temporarily attached for permitting no injury of the integrated circuits 10.
This is followed by, as shown in FIG. 1B, bonding a supporting member 13 by a coat of adhesive 12, such as a die attach film (DAF), to the back side of the thinned semiconductor substrate 10 (Step #2). The supporting member 13 may be a metal plate such as Fe—Ni alloy or stainless alloy. The supporting member 13 is preferably 100 μm in the thickness and may arbitrarily be determined depending on the requirement of the surface mount arrangement.
The supporting member 13 has either its thinned regions which are reduced in the thickness or its void regions which are open between both sides thus having no thickness, the regions being positioned just beneath the scribing lines between the integrated circuits 11. The thickness of the thinned regions may arbitrarily be determined depending on the final design pattern arrangement. In this embodiment, the thickness of the thinned regions is from ½ to ⅕ of the thickness of the supporting member. It is assumed that the thinned region or void region of the supporting member 13 is each denoted by the thinned region 14 or void region 14, when the supporting member 13 has either the thinned region or the void region. When both the thinned region and the void region are provided at once in the supporting member 13, they are denoted by 14a and 14b respectively for ease of the understanding without confusion.
FIG. 3 is diagrams illustrating a design pattern of the supporting member 13 along with the primary side of the semiconductor substrate 10 on which the integrated circuits 11 are arrayed. More particularly, FIG. 3A is a schematic illustrates an array of the integrated circuits 11 provided on the semiconductor substrate 10 at perspective elevation while FIG. 3B illustrates the supporting member 13 corresponding to the array at perspective elevation.
As shown in FIG. 3A, the scribing lines 21 extend lengthwise and widthwise to separate the integrated circuits 11 provided on the primary side of the semiconductor substrate 10. Either the thinned regions or void regions 14 of the supporting member 13 extend partially or entirely beneath the scribing lines 21 on the primary side of the substrate 10. It is also assumed that a region of the supporting member 13 just beneath each integrated circuit chip on the semiconductor substrate 10 defined by the scribing lines 21 is termed “supporting block region” and the other regions including the void regions) than the supporting block regions which are thinner than the supporting block regions are termed “regions to be thinned”. In other words, the supporting member 13 has the thinned regions 14 which are thinner than the supporting block regions or the void regions 14 which is an opening in the supporting member at least in a part of the regions 22 (the outer peripheral region of the supporting block regions) which is located correspondingly beneath the scribing lines 21 on the primary side of the substrate 10. In the supporting member 13 shown in FIG. 3B, the thinned region or void region 14 is assigned to each corner of the outer peripheral region of the supporting block regions.
FIG. 4 illustrates schematic cross sectional views of the supporting member 13 including the regions to be thinned. FIG. 4A shows that the regions to be thinned in the supporting member are clear. FIG. 4B shows that the regions to be thinned are formed by providing a recess in one side of the supporting member and being thinner than the supporting block regions. FIG. 4C shows that the regions to be thinned are formed by providing a pair of recesses in both the sides of the supporting member respectively and being thinner than the supporting block regions. The supporting member 13 may be implemented by selecting one of the structures of the regions to be thinned shown in FIGS. 4A to 4C.
At Step #2, the supporting member 13 is bonded to the back side of the semiconductor substrate 10. Preferably, when the supporting member 13 is configured as shown in FIG. 4B, its recessed side (at the upper in the FIG. 4B) is joined to the back side of the semiconductor substrate 10. Alternatively, the other side may be bonded to the back side.
Then, as shown in FIG. 1C, a dicing tape 15 (or a dicing sheet, the dicing tape used for the description hereinafter) is attached to the back side of the supporting member 13 to secure the entire assembly at stableness (Step #3).
As shown in FIG. 1D, the assembly including the integrated circuits 11, the semiconductor substrate 10, the DAF 12, and the supporting member 13 is cut (diced) continuously along the scribing lines between the integrated circuits 11. The dicing may be conducted at once or in steps. Since the supporting member 13 in this embodiment is made from an Fe—Ni alloy, it is cut using a CBN (cubic boron nitride) blade.
As shown in FIG. 1E, the dicing tape 15 is removed from the back side of the supporting member 13 on each integrated circuit chip (Step #5). As the result, the integrated circuit chip remains supported at the back side with the supporting member 13 (Step #6).
FIG. 5 illustrates schematic views of the integrated circuit chip manufactured by the foregoing steps. FIG. 5A is a schematic top view while FIG. 5B is a schematic perspective view. The chip shown in FIG. 5 is featured with the regions to be thinned remaining open.
FIG. 5 illustrates the integrated circuit chip separated with no cutting margin in an ideal dicing action at Step #4 for ease of the understanding. In actual practice, there are some cutting margins and the four sides of the integrated circuit chip are apparently moved inward by the cutting margins. As will be understood, illustrations shown in FIGS. 7, 9, 11, 13, and 19, described later, result from the ideal dicing action.
As shown in FIG. 3B, each supporting block region in the supporting member 13 in this embodiment is defined at every corners by the void regions. Accordingly, as shown in FIG. 5, the supporting member 13 is not present at each corner of the integrated circuit chip. Hence, the supporting member 13 is smaller in the area size than the semiconductor substrate 10 as there is a discrepancy in the shape at each corner between the supporting member 13 and the semiconductor substrate 10.
As its back side has been joined directly with the semiconductor supporting member 13, the integrated circuit chip is subjected to a known flip chip technique for the surface mounting. After the post steps including an inspection step, the semiconductor device will be finished.
According to the inventive method, at the cutting step of Step #4, since the particular regions of the supporting member 13 including the cutting lines are included at least partly in the regions to be thinned, they remain open as voids or their thickness is smaller than that of the supporting block regions. Therefore, the force required for cutting the supporting member can be lower than that for cutting a supporting member with the conventional thickness. Also, as the supporting member to be cut apart is minimized in the area at the cross section subjected to the cutting, it can create a less amount of the burrs than the conventional supporting member.
The supporting member 13 is not limited to the design pattern shown in FIG. 3B but may be provided with any applicable pattern. Other applicable design patterns of the supporting member 13 will be explained referring to FIGS. 6 to 13.
FIGS. 6, 8, 10, and 12 are views illustrating the other applicable design patterns of the supporting member 13 in combination with the semiconductor substrate 10 on the primary side of which an array of the integral circuits 11 are arrayed as similar to that shown in FIG. 3 for ease of the description. (Equal to FIG. 3, denoted by A is a schematic view at perspective elevation of the semiconductor substrate 10 on the primary side of which the integral circuits 11 are arrayed and denoted by B is a schematic view at perspective elevation of the supporting member 13.)
A supporting member 13 shown in FIG. 6B is different in the design pattern from that shown in FIG. 3B, in which the thinned or void regions 14 are provided at a part of the outer peripheral region of the supporting block region excluding the corner regions. FIG. 7 illustrates schematic views of an integrated circuit chip manufactured using the supporting member 13 of this design pattern by the foregoing steps. Similar to FIG. 5, FIGS. 7A and 7B are a schematic top view and a schematic perspective view respectively, where the regions to be thinned are the void regions. In particular, the void regions are provided at a part of the outer peripheral region of each supporting block region of the supporting member 13 excluding the corner regions, like those shown in FIG. 6B. As apparent from FIG. 7, a resultant integrated circuit chip has the void region of the supporting member 13 allocated along its four sides but not at its corners and allows its supporting member 13 to be smaller in the area size than the semiconductor substrate 10.
A supporting member 13 shown in FIG. 8B is similar in the design pattern to that shown in FIG. 3B in which the thinned or void regions 14 are provided at all the four corners of the outer peripheral region of each supporting block region but different in the shape of the thinned or void regions. More specifically, while the thinned or void regions 14 at the corners in the design pattern shown in FIG. 3B are arranged of an L shape, they are arranged of a circular or oval shape in the design pattern shown in FIG. 8B. FIG. 9 illustrates schematic views of an integrated circuit chip manufactured using the supporting member 13 of this design pattern by the foregoing steps. Similar to FIG. 5, FIGS. 9A and 9B are a schematic top view and a schematic perspective view respectively, where the regions to be thinned are the void regions. The void regions 14 are provided at the four corners of the outer peripheral region of each supporting block region of the supporting member 13, as shown in FIG. 8B. As apparent from FIG. 9, a resultant integrated circuit chip has the void regions of the supporting member 13 allocated at its corners and allows its supporting member 13 to be smaller in the area size than the semiconductor substrate 10.
A supporting member 13 shown in FIG. 10B is arranged in which the thinned regions 14 are provided extending along all the outer peripheral region of each supporting block region as positioned correspondingly beneath the scribing lines 21. FIG. 11 illustrates schematic views of an integrated circuit chip manufactured using the supporting member 13 of this design pattern by the foregoing steps. FIG. 11A is a schematic top view and FIG. 11B is a schematic perspective view. As apparent from FIG. 10B, the thinned regions 14 extend along all the outer peripheral region of each supporting block region on the supporting member 13 and a resultant integrated circuit chip shown in FIG. 11 has the supporting member 13 thinned along the outer peripheral region thereof.
A supporting member 13 shown in FIG. 12B carries a combination of the design pattern shown in FIG. 3B and the design pattern shown in FIG. 6B, in which the void regions 14b are provided at all the four corners of the outer peripheral region of each supporting block region while the thinned regions 14a are provided partially along the outer peripheral region, other than the corners, of the same supporting block region. FIG. 13 illustrates schematic views of an integrated circuit chip manufactured using the supporting member 13 of this design pattern by the foregoing steps. FIG. 13A is a schematic top view and FIG. 13B is a schematic perspective view. The void regions 14b are provided at the four corners of the outer peripheral region of each supporting block region of the supporting member 13, as shown in FIG. 12B. As apparent from FIG. 13, a resultant integrated circuit chip has the void regions 14b of the supporting member 13 allocated at its corners while the thinned regions 14a allocated partially along the outer peripheral region and thus allows its supporting member 13 to be thinned along partially the outer peripheral region other than the corners.
Although the design pattern shown in FIG. 12 carries the void regions 14b provided at the four corners of the outer peripheral region of each supporting block region and the thinned regions 14a provided partially along the outer peripheral region, other than the corners, of the same, the void region 14b and the thinned region 14a may be replaced at the positional relationship by each other. While either the thinned region 14a or the void region 14b is provided partially along the outer peripheral region of the supporting block region on the supporting member 13 in the design pattern shown in FIG. 12, it may be replaced by a region with normal thickness (of which the thickness is equal in the thickness at the center of the supporting block region of the supporting member 13).
The design patterns shown in FIGS. 3, 6, 8, 10, and 12 are illustrative but not of limitations.
Second Embodiment
The second embodiment of the present invention (referred to as “this embodiment” hereinafter) will be described referring to FIGS. 14 and 15. FIG. 14 is a schematic cross sectional view of steps, FIG. 14A to FIG. 14F, for manufacturing a semiconductor device of this embodiment. FIG. 15 is a flowchart showing the steps of FIG. 14 and the following description will be made using the steps numbered in FIG. 15.
This embodiment is different in the order of the steps from the first embodiment. Like components are denoted by like numerals as those in the first embodiment, for example, the supporting member 13, and will be described in no more detail.
As shown in FIG. 14A, the flowchart starts with providing two or more integrated circuits 11 on the primary side of a semiconductor substrate 10 made of a silicon material or the like (Step #11), similar to Step #1 of the first embodiment. Then, the semiconductor substrate 10 is thinned by, for example, polishing its back side.
This is followed by, as shown in FIG. 14B, attaching a dicing tape 15 to the primary side of the semiconductor substrate 10 where the integral circuits 11 are arrayed to secure the entire assembly at stableness (Step #12).
As shown in FIG. 14C, the integrated circuits 11 and the semiconductor substrate 10 are cut (diced) at once along the cutting lines corresponding to the scribing lines between the integrated circuits 11, using a diamond blade or the like (Step #13).
Then, as shown in FIG. 14D, the supporting member 13 carrying a pattern of the void or thinned regions 14 is bonded by an adhesive 12 to the back side of the semiconductor substrate 10 (Step #14). The adhesive 12 and the material and construction of the supporting member 13 are identical to those of the first embodiment.
As shown in FIG. 14E, the supporting member 13 and the adhesive 12 is cut apart along the cutting lines positioned correspondingly beneath the scribing lines between the integrated circuits 11 (Step #15).
As shown in FIG. 14F, the dicing tape 15 is removed from each integrated circuit chip joined at the back side to the supporting member 13 (Step #16). As the result, the integrated circuit chip remains supported at the back side with the supporting member 13 (Step #17). When its back side has been joined directly with the semiconductor supporting member 13, the integrated circuit chip is subjected to a known flip chip technique for the surface mounting. After the post steps including an inspection step, the semiconductor device of this embodiment will be finished.
The semiconductor device of this embodiment manufactured by the above described steps, like that of the first embodiment, at the cutting step of Step #15, allows the particular regions of the supporting member 13 including the cutting lines are included at least locally in the regions to be thinned, they remain open as voids or their thickness is smaller than that of the supporting block regions. Therefore, the force required for cutting the supporting member can be lower than that for cutting a conventional supporting member with uniform thickness. Also, as the supporting member 13 to be cut apart is minimized in the area at the cross section subjected to the cutting, it can create a less amount of the burrs than the conventional supporting member.
Third Embodiment
The third embodiment of the present invention (referred to as “this embodiment” hereinafter) will be described referring to FIGS. 16 to 19. FIG. 16 is a schematic cross sectional view of steps, FIG. 16A to FIG. 16E, for manufacturing a semiconductor device of this embodiment. FIG. 17 is a flowchart showing the steps of FIG. 16 and the following description will be made using the steps numbered in FIG. 17. FIG. 18 illustrates a design pattern of the supporting member 13 in this embodiment. FIG. 19 is a schematic view of an integrated circuit chip manufactured by the steps of this embodiment, using the supporting member 13 of the design pattern shown in FIG. 18.
This embodiment is different in the order of the steps from the first and second embodiments. The supporting member 13 bonded to the semiconductor substrate 10 in either the first or second embodiment remains a plate material before subjected to the cutting step although having a pattern of the void or thinned regions 14. In this embodiment, the supporting member is separated into the supporting block regions before subjected to the step of bonding to the semiconductor substrate 10. Like components are denoted by like numerals as those in the first and second embodiments and will be described in no more detail.
As shown in FIG. 16A, the flowchart starts with attaching a dicing tape 15 to a plate material 13a which becomes the supporting member 13 later to secure their assembly at stableness (Step #21).
Then as shown in FIG. 16B, the plate material 13a is subjected to photo-lithography and etching actions for separation along the cutting lines positioned correspondingly beneath the scribing lines between the integrated circuits 11 on the primary side of the semiconductor substrate 10 to which the supporting member 13 is bonded at the later step (Step #22). As the result, the plate material 13a is cut into the supporting block regions which turn to the supporting members 13, each having the void regions 14 at the entire outer peripheral region. Since the supporting members 13 are attached with the dicing tape 15, they are not separated but remain in an array. Although the supporting members remain attached to, but is not limited to, the dicing tape 15 in this embodiment for avoiding the dropping off, they may be held together by any applicable technique.
This is followed by, as shown in FIG. 16C, bonding the supporting members 13 by an adhesive 12 to the back side of the semiconductor substrate 10 on which the integrated circuits 11 are arrayed on the primary side (Step #23). Particularly before being bonded to the semiconductor substrate 10, the supporting members 13 of the supporting block regions are aligned with the back side of the integrated circuit chips of which the positions are defined by the scribing lines extending between the integrated circuits 11.
Then as shown in FIG. 16D, the integrated circuits 11 and the semiconductor substrate 10 bonded together by the adhesive 12 are cut at once along the scribing lines between the integrated circuits 11, using a diamond blade or the like (Step #24).
As shown in FIG. 16E, the dicing tape 15 is removed from an array of the integrated circuit chips bonded at the back side with the supporting members 13 (Step #25). The integrated circuit chip is hence separated as remaining supported at the back side with the supporting member 13 (Step #26). When its back side has been joined directly with the supporting member 13, the integrated circuit chip is subjected to a known flip chip technique for the surface mounting. After the post steps including an inspection step, the semiconductor device of this embodiment will be finished.
FIG. 18 illustrates a design pattern of the supporting members 13 in this embodiment together with the semiconductor substrate 10 on which the primary side the integrated circuits 11 are arrayed. FIG. 18A is a schematic view at perspective elevation of the semiconductor substrate 10 on which the integrated circuits 11 are arrayed and FIG. 18B is a schematic view at perspective elevation of the corresponding pattern of the supporting members 13. In this embodiment, the part located correspondingly beneath the scribing lines 21 are removed from the plate material 13a by etching to form the supporting members 13 at Step #22, and the supporting members 13 remain attached to the dicing tape 15 for avoiding them from being dropped off. More particularly, each of the supporting members 13 has the void region 14 at all the outer peripheral region of the supporting block region.
FIG. 19 illustrates schematic views of an integrated circuit chip manufactured using the supporting member 13 of the design pattern shown in FIG. 18. FIG. 19A is a schematic top view and FIG. 19B is a schematic perspective view. The void regions 14 are provided at all the outer peripheral region of each supporting block region of the supporting member 13, as shown in FIG. 18B. As apparent from FIG. 19, a resultant integrated circuit chip does not have the supporting member 13 at its outer peripheral region.
The semiconductor device of this embodiment is manufactured by the above described steps where the plate material which will become the supporting members 13 is attached with the dicing tape and separated by etching into the supporting block regions corresponding to their respective integral circuit chips and then the semiconductor substrate on which the integrated circuit is disposed is joined with each of the supporting members. Accordingly, the generation of burrs can be minimized as the step of cutting the full size of the supporting member is eliminated.
The etching step at Step #22 in this embodiment is adapted for removing the cutting regions of the plate material 13a positioned correspondingly beneath the scribing lines between the integrated circuits 11 to separate the plate material 13a into the supporting block regions, to form the supporting member 13 of which each supporting block region has the void region 14 at all the outer peripheral region. Alternatively, the cutting regions of the strips 13a corresponding the scribing lines between the integrated circuits 11 are etched to a depth to develop the thinned regions without completely separating the supporting block regions. In the latter case, the supporting member 13 is identical in the construction to that shown in FIG. 10B where the supporting member 13 has the thinned regions 14 at all the outer peripheral region of each supporting block region.
More specifically, this can be done by bonding the substrate 10 to the primary side of the supporting member 13 at Step #23 and then cutting the assembly of the integrated circuit 11, the substrate 10, the adhesive 12, and the supporting member 13 at once along the scribing lines at Step #24. Accordingly, a resultant integrated circuit chip is provided as remaining supported at the back side with the supporting member 13. This is different from the procedure of the third embodiment and requires an extra step of cutting the supporting member 13. However, as the supporting member 13 to be cut apart has been thinned along the cutting lines, like that of the first or second embodiment, the force required for cutting the supporting member can be lower than that for cutting a conventional supporting member with uniform thickness. Also, as the supporting member 13 to be cut apart is minimized in the area at the cross section subjected to the cutting, it can create a less amount of the burrs than the conventional supporting member.
Although the present invention has been described in terms of the preferred embodiment, it will be appreciated that various modifications and alternations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.
Patent Application
20080032485
