This invention is based on Japanese Patent Application No. 2003-351076, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, specifically to a structure and a manufacturing method of a high voltage MOS transistor.
2. Description of the Related Art
The high voltage MOS transistor attains a high drain withstand voltage by placing the N−-type drain layer 55a adjacent the gate electrode 52 and placing the N+-type drain layer 55b away from the gate electrode 52.
Further description on such a high voltage MOS transistor is found, for example, in Japanese Patent Publication No. H05-218070.
The conventional high voltage MOS transistor described above, however, has a problem that an operational withstand voltage (a drain withstand voltage when the MOS transistor is turned on) is low. Especially when a gate-source voltage Vgs is low and a drain-source voltage Vds is high, an electric field converges in a surface at an edge of the drain layer to cause a so-called impact ionization phenomenon in which a channel current flows through the region where the electric field converges. This induces a large substrate current Isub, leading to a reduction in the operational withstand voltage.
This invention is directed to a high voltage MOS transistor with reduced substrate current Isub during operation stage. A semiconductor device of this invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate through a gate insulation film, a low impurity concentration drain layer formed in a surface of the semiconductor substrate to overlap the gate electrode, a high impurity concentration drain layer formed in the surface of the semiconductor substrate and a source layer formed in the surface of the semiconductor substrate. This configuration results in a formation of a depleted surface layer at the low impurity concentration drain layer below the gate electrode when a drain-source voltage Vds higher than a gate-source voltage Vgs is applied to the high impurity concentration drain layer. The invention is also directed to a method of manufacturing a semiconductor device. The method includes forming a gate insulation film on a semiconductor substrate, forming a low impurity concentration drain layer in a surface of the semiconductor substrate, forming a gate electrode on the gate insulation film to overlap the low impurity concentration drain layer and forming a high impurity concentration drain layer in the surface of the semiconductor substrate.
Next, embodiments of this invention will be described. Semiconductor devices and their manufacturing methods according to the embodiments of this invention will be explained referring to the figures hereinafter.
A first embodiment of this invention will be described, referring to
A gate insulation film 2 is formed on a surface of a P-type semiconductor substrate 1 (e.g. a P-type silicon substrate) by thermal oxidation, for example, as shown in
Next, a gate electrode 5 is formed on the gate insulation film 2 so that the gate electrode overlaps the N−-type source layer 3a and the N−-type drain layer 4a, as shown in
Next, a high dose of N-type impurity ions such as phosphorus is implanted into the surface of the P-type semiconductor substrate 1 to form an N+-type source layer 3b and an N+-type drain layer 4b, each adjacent a corresponding edge of the gate electrode 5, as shown in
Operation of the high voltage MOS transistor will be described hereafter referring to
A surface depletion layer 7 is induced in a surface of the N−-type drain layer 4a overlapping the gate electrode 5, when the drain-source voltage Vds is higher than the gate-source voltage Vgs (Vds>Vgs). Consequently, a channel current Ie (electron current) of the high voltage MOS transistor flows through a deep region of the N−-type drain layer 4a under the surface depletion layer 7 to avoid flowing through the surface region at the edge of the N−-type drain layer 4a where the electric field converges. This results in a reduced substrate current Isub and an improved operational withstand voltage.
Next, a second embodiment of this invention will be described referring to
Since the N+-type drain layer 4b is placed away from the edge of the gate electrode 5, the drain leakage current GIDL due to the strong electric field at the edge of the gate electrode is prevented from occurring, leading to further enhancement of the operational withstand voltage.
Although the source layer 3 has a low impurity concentration layer, i.e. the N−-type source layer 3a in the first and the second embodiments, the source layer 3 may be made of the N+-type source layer 3b only.
According to this invention, the low impurity concentration drain layer is formed in the surface of the semiconductor substrate below the gate electrode to overlap the gate electrode so that the surface of the low impurity concentration drain layer under the gate electrode is depleted when the drain-source voltage Vds higher than the gate-source voltage Vgs is applied to the drain electrode. Since the channel current of the MOS transistor flows through the low impurity concentration drain layer under the surface depletion layer to avoid flowing through the surface region at the edge of the low impurity concentration drain layer where the electric field converges, the substrate current Isub is reduced and the operational withstand voltage is enhanced. Since the channel current flows beneath the depletion layer, that is, away from the surface of the semiconductor substrate, surface scattering of current carriers is reduced to improve drive characteristics of the transistor.
Number | Date | Country | Kind |
---|---|---|---|
2003-351076 | Oct 2003 | JP | national |