Semiconductor device and manufacturing method thereof

Abstract

In a semiconductor device having a concave-type capacitor, HSG silicon is formed on a side surface of a lower electrode while no HSG silicon is formed on a bottom of the lower electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing an outline of a related manufacturing process of a concave-type capacitor;

FIG. 2 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 3 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 4 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 5 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 6 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 7 is a cross-sectional view showing an outline of the related manufacturing process of the concave-type capacitor;

FIG. 8 is a cross-sectional view showing an outline of a manufacturing process of a concave-type capacitor according to the present invention;

FIG. 9 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention;

FIG. 10 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention;

FIG. 11 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention;

FIG. 12 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention;

FIG. 13 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention; and

FIG. 14 is a cross-sectional view showing an outline of the manufacturing process of the concave-type capacitor according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

An embodiment will be described with reference to FIGS. 8 to 14, which are cross-sectional views showing an outline of a manufacturing process of a concave-type capacitor in the first example.

As shown in FIG. 8, a contact hole is formed in a contact interlayer insulating film 1. Then, a conductive material of a doped polysilicon film is embedded as a pad material into the contact hole. The conductive material is flattened by CMP, and a contact pad is patterned by the use of a photoresist. Subsequently, a contact pad 21 is formed by dry etching. The contact pad 21 includes a contact plug portion connected to a diffusion layer (not shown) of a cell transistor and a contact pad portion on an upper surface of the contact interlayer insulating film 1. The contact pad portion of the contact pad 21 is formed so as to fully cover the contact plug portion (FIG. 9).

Next, a cylinder interlayer insulating film 2 is deposited on the contact interlayer insulating film 1, and a photoresist is patterned to define an area in which a storage node is to be formed. Then, a storage node hole C2 having a concave shape is formed in the cylinder interlayer insulating film 2 by dry etching (FIG. 10). The size of a bottom of the storage node hole C2 is smaller than that of the contact pad 21. The storage node hole C2 is formed so that the bottom of the storage node hole C2 is located inside of the contact pad 21. Accordingly, it is desirable that the center of the storage node hole C2 be approximately aligned with the center of the contact pad 21. Subsequently, a doped polysilicon film 12 and a non-doped amorphous silicon film 13, which are to be a storage node electrode, are deposited as shown in FIG. 11.

Next, the doped polysilicon film 12 and the non-doped amorphous silicon film 13 are etched by anisotropic dry etch-back so as to form a storage node electrode separated from other storage node electrodes. This process etches a portion of the doped polysilicon film 12 and the non-doped amorphous silicon film 13 located on an upper surface of the cylinder interlayer dielectric film 2 and on a surface of the contact pad 21. Thus, the doped polysilicon film 12 and the non-doped amorphous silicon film 13 are left only on side surfaces of the storage node hole C2. Accordingly, the contact pad 21 is located on the bottom of the concave-type storage node electrode while the doped polysilicon film 12 and the non-doped amorphous silicon film 13 are located on the side surfaces of the concave-type storage node electrode (FIG. 12).

Next, a HSG treatment is performed on the non-doped amorphous silicon film 13 in order to increase the capacitance value of the capacitor. In this event, HSG silicon does not grow on the bottom of the storage node electrode because the pad material of the doped polysilicon is exposed on the bottom of the storage node electrode. Only the non-doped amorphous silicon film 13 located on the side surfaces of the storage node hole C is selectively subjected to the HSG treatment and thus converted into HSG silicon 14 (FIG. 13). Even if the HSG silicon is further enlarged to increase a capacitance value of the capacitor, the bottom of the storage node electrode is not clogged by the HSG silicon because no HSG silicon grows on the bottom of the storage node electrode. Accordingly, the particle diameter of the HSG silicon can be increased without causing the bottom of the storage node electrode to be clogged by the HSG silicon. A surface area of the capacitor electrode can be increased with the large HSG silicon (FIG. 14).

After the formation of the storage node electrode, a capacitor insulating film is formed. Since the bottom of the storage node electrode is not clogged by the HSG silicon, a gas for deposition of the capacitor insulating film can be introduced uniformly into the storage node electrode. Consequently, the capacitor insulating film can be deposited with a uniform film thickness. Furthermore, a conductive film is deposited so as to face the storage node electrode, and patterning is carried out so as to form a counter electrode opposed to the storage node electrode. The counter electrode is connected to a reference potential of the memory cell of the DRAM. Thus, the capacitor according to the present invention is formed between the storage node electrode connected to the diffusion layer of the cell transistor in the memory cell and the counter electrode connected to the reference potential.

In a capacitor according to the present invention, a hole for electrodes is formed in a cylinder interlayer insulating film. A storage node electrode (lower electrode), a capacitor insulating film, and a counter electrode (upper electrode) are formed within the hole. Although the above description relates to a DRAM memory cell, the present invention is not limited to a DRAM. For example, the present invention is applicable to any general-purpose capacitor having a lower electrode and an upper electrode that correspond to the aforementioned storage node electrode and counter electrode, respectively.

As described above, a contact pad structure of doped polysilicon is provided on a bottom of a lower electrode of a concave-type capacitor. As a consequence, a HSG treatment is performed only on side surfaces of the lower electrode while no HSG treatment is performed on the bottom of the lower electrode. Since no HSG treatment is performed on the bottom of the lower electrode, the film thickness of a capacitor insulating film can be made uniform, and a capacitor leakage current can be prevented. Therefore, with high reliability of the capacitor insulating film having no variations in film thickness, it is possible to obtain a semiconductor device with high reliability and a method of manufacturing such a semiconductor device.

Although the present invention has been specifically described based on the illustrated example, the present invention is not limited to the illustrated example. It should be understood that various changes and modifications may be made therein without departing from the spirit of the present invention and are thus included in the scope of the present invention.

Claims

1. A semiconductor device having a concave-type capacitor, wherein: HSG silicon is formed on a side surface of a lower electrode while no HSG silicon is formed on a bottom of the lower electrode.

2. The semiconductor device according to claim 1, wherein: the bottom of the lower electrode is formed by a contact pad provided on a contact plug and on an interlayer insulating film.

3. The semiconductor device according to claim 2, wherein: the bottom of the lower electrode is smaller than the contact pad and is located inside the contact pad.

4. The semiconductor device according to claim 3, wherein: the contact pad is connected to the contact plug connected to a diffusion layer and is formed by the same conductive material as the contact plug.

5. The semiconductor device according to claim 4, wherein: the contact pad is formed of doped polysilicon.

6. A method of manufacturing a semiconductor device, comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate;forming a contact hole in the first interlayer insulating film;depositing a conductive film so as to fill the contact hole with the conductive film;forming a contact plug and a contact pad;depositing a second interlayer insulating film;forming a storage node hole extending to the contact pad;depositing a layer including at least non-doped amorphous silicon as a lower electrode of a capacitor;forming the lower electrode of the capacitor by dry etch-back;attaching a core onto a surface of the non-doped amorphous silicon;performing an HSG treatment so that no HSG silicon is formed on a bottom of the lower electrode; andforming a capacitor insulating film and an upper electrode of the capacitor.

7. The method according to claim 6, wherein: doped polysilicon is deposited as an underlayer of the non-doped amorphous silicon for the lower electrode of the capacitor.

8. The method according to claim 7, wherein: the forming step of the lower electrode by dry etch-back comprises etching and removing the doped polysilicon and the non-doped amorphous silicon from a bottom of the storage node hole so as to expose a portion of a surface of the contact pad.