Patent Application
20060284283
1. Field of the Invention
The present invention relates to a Zener diode, and more particularly relates to a Zener diode incorporated in a semiconductor deice having a MOS (metal oxide semiconductor) transistor or the like.
2. Description of the Prior Art
In forming an impurity diffusion region in a semiconductor deice by ion implantation, thermal treatment is carried out for activating and diffusing the implanted impurity. Meanwhile, in association with miniaturization in element size, the impurity diffusion region must be miniaturized, and accordingly, the temperature for the thermal treatment must be lowered for preventing the implanted impurity from excessive diffusion.
For miniaturization in element size of the above semiconductor device, a small-sized and large-current capacity Zener diode has been proposed as a miniaturized Zener diode (see Japanese Utility Model Application Laid-open Gazette No. 6-2720A, for example).
The n+ impurity region 202 is larger than the p+ impurity region in size in the plane direction and the depth direction. This allows the p+n+ junction plane to be flat, suppressing a local increase in current density. Thus, a small-sized large-current capacity Zener diode can be obtained.
However; when low-temperature thermal treatment is carried out for restraining impurity diffusion for the purpose of element size miniaturization in the conventional Zener diode shown in
In view of the above problems, the present invention has its object of providing a Zener diode and a method for manufacturing it which can prevent leakage current and resistance of an impurity region from increasing under miniaturization.
To attain the above object, a first semiconductor device according to the present invention is a semiconductor including a semiconductor substrate and a Zener diode formed on the semiconductor substrate, wherein the Zener diode includes: a first conductivity type semiconductor region and a second conductivity type semiconductor region which are formed so as to form pn junction in the semiconductor substrate; an insulating film for covering a junction part of the first conductivity type semiconductor region and the second conductivity type semiconductor region; a first electrode formed on the first conductivity type semiconductor region so as to be electrically connected with the first conductivity type semiconductor region; and a second electrode formed on the second conductivity type semiconductor region so as to be electrically connected with the second conductivity type semiconductor region, wherein the second conductivity type semiconductor region has an impurity concentration distribution which is a combination of a first impurity concentration diffusion distribution having first diffusion depth and first peak concentration and a second impurity diffusion distribution having second diffusion depth shallower than the first diffusion depth and second peak concentration higher than the first peak concentration, and the first impurity concentration distribution is higher than the second impurity concentration distribution in concentration at the junction part.
In the first semiconductor device according to the present invention, the second conductivity type semiconductor region has the impurity concentration distribution which is a combination of the first impurity concentration distribution having lower concentration and deeper diffusion depth and the second impurity concentration distribution having higher concentration and shallower diffusion depth, and the concentration at the junction part of the first conductivity type semiconductor region and the second conductivity type semiconductor region is defined by the low-concentration first impurity concentration distribution in the second conductivity type semiconductor region. Accordingly, the pn junction part, on which leakage current concentrates, can have impurity concentration lower than that of the conventional one even in the case where the impurity layers of the Zener diode are formed by low-temperature thermal treatment for the purpose of element size miniaturization, reducing leakage current. Also, the impurity concentration in the vicinity of the substrate surface in the second conductivity type semiconductor region is defined by the high-concentration second impurity concentration distribution, resulting in a lowering in resistance of the second conductivity type semiconductor region and a lowering in contact resistance between the second conductivity type semiconductor region and the electrode.
A second semiconductor device according to the present invention is a semiconductor integrated circuit device in which a Zener diode and a CMOS (complementary metal oxide semiconductor) circuit or the like are hybrided on a single semiconductor substrate, wherein each of a p+ source region and a p+ drain region of a p-channel field effect transistor and a p+ anode region of the Zener diode has an impurity concentration distribution which is a combination of a first impurity concentration distribution and a second impurity concentration distribution having diffusion depth and peak concentration shallower and higher than the first impurity concentration distribution, and the first impurity concentration distribution is higher than the second impurity concentration distribution in concentration at a junction part of the p+ anode region and an n+ cathode region.
In the second semiconductor device according to the present invention, similar to the first semiconductor device, the pn junction part, on which leakage current concentrates, can have impurity concentration lower than the conventional one even in the case where impurity layers of the Zener diode are formed by low-temperature thermal treatment for the purpose of element size miniaturization, reducing leakage current of the Zener diode. Accordingly, this prevents an increase in impurity concentration at the pn junction part by low-temperature thermal treatment, and hence, the respective p+ impurity layers in the source region and the drain region of the p-channel filed effect transistor can be formed by low-temperature thermal treatment, implementing further element size miniaturization with impurity diffusion restrained. Also, the impurity concentration in the vicinity of the substrate surface in the p+ impurity layer in the anode region of the Zener diode is defined by the high-concentration second impurity concentration distribution, lowering both the resistance of the anode region and the contact resistance between the anode region and the electrode.
In manufacturing the second semiconductor device of the present invention, that is, a semiconductor integrated circuit device in which a Zener diode and a COMS circuit or the like are hybrided on a single substrate, the impurity layers in the cathode region and the anode region of the Zener diode are formed in the same step as the step of forming the impurity layers of the source regions and the drain regions of the CMOS circuit, so that the Zener diode can be hybrided without increasing the number of manufacturing steps.
As described above, in the Zener diode formed on the semiconductor substrate according to the present invention, the pn junction part, on which leakage current concentrates, can have low concentration, reducing leakage current.
Further, according to the present invention, in the semiconductor integrated circuit device in which a Zener diode and CMOS circuit or the like are hybrided on a single substrate, the pn junction part, on which leakage current of the Zener diode concentrates, can have low concentration, reducing leakage current of the Zener diode. Further, the p+ impurity layers in the source region and the drain region of the p-channel field effect transistor can be formed at low temperature, implementing element size reduction while restraining impurity diffusion. Also, the impurity layers in the cathode region and the anode region of the Zener diode are formed in the same step as the step of forming the impurity layers in the source region and the drain region of the CMOS circuit, enabling hybridization of the Zener diode without increasing the number of manufacturing steps.
In consequence, the semiconductor device and the semiconductor device manufacturing method according to the present invention are useful for realizing a low-leakage Zener diode. Particularly, in the case where the present invention is applied to a semiconductor integrated circuit device in which a Zener diode and a CMOS circuit or the like are hybrided on a single substrate, the present invention is much useful because an effect of element size miniaturization with impurity diffusion restrained and an effect of hybridization of a Zener diode without increasing the number of manufacturing steps can be obtained in addition to the effect of realizing a low-leakage Zener diode.
A semiconductor device and a method for manufacturing it according to Embodiment 1 of the present invention will be described below with reference to the accompanying drawings.
As shown in
Specifically, the semiconductor substrate 1 is formed of an n-type silicon substrate having an impurity concentration of approximately 1×1016 to 1×1017 cm−3, for example. The impurity concentration distribution of the n-type semiconductor layer 2 is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 1×1020 to 5×1020 cm−3 and of which diffusion depth is approximately 0.3 to 0.5 μm, for example. The p-type impurity concentration distribution of the p-type semiconductor layer 3 is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 7×1018 to 3×1019 cm−3 and of which diffusion depth is approximately 0.6 to 0.9 μm, for example. The p-type impurity concentration distribution of the p-type semiconductor layer 4 is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 3×1019 to 1×1020 cm−3 and of which diffusion depth is approximately 0.3 to 0.5 μm, for example. The n-type impurity concentration distribution of the n-type semiconductor layer 2 and the p-type impurity concentration distributions of the p-type semiconductor layers 3 and 4 overlap with each other in the range of approximately 1 to 2 μm in the horizontal direction. Further, the impurity concentration at the pn junction part of the n-type semiconductor layer 2 and the p-type semiconductor layers 3, 4 (where the n-type impurity concentration and the p-type impurity concentration are in equilibrium) is approximately 1×1018 to 5×1018 cm−3, for example. The insulating film 5 is formed of a silicon oxide film having a thickness of approximately 100 nm to 2 μm, for example. The cathode electrode wiring 6a and the anode electrode wiring 6b are made of Al—Si—Cu alloy of which main component is Al and which has approximately the same thermal conductivity as Al, for example.
One of the significant features of the present embodiment lies in that the p-type semiconductor region formed of the p-type semiconductor layer 3 and the p-type semiconductor layer 4 has an impurity concentration distribution which is a combination of a first p-type impurity concentration distribution (defining the impurity concentration distribution of the p-type semiconductor layer 3) having first diffusion depth and first peak concentration and a second p-type impurity concentration distribution (defining the impurity concentration distribution of the p-type semiconductor layer 4) having second diffusion depth shallower than the first diffusion depth and second peak concentration higher than the first peak concentration. Wherein, the first p-type impurity concentration distribution is higher than the second p-type impurity concentration distribution in concentration at the pn junction part.
In the present embodiment, the region where the concentration in the first p-type impurity concentration distribution is higher than the concentration in the second p-type impurity concentration distribution serves as the p-type semiconductor layer 3 while the region where the concentration of the second p-type impurity concentration distribution is higher than the concentration in the first p-type impurity concentration distribution serves as the p-type semiconductor layer 4. Accordingly, the pn junction part is a junction part of the low-concentration p-type semiconductor layer 3 and the n-type semiconductor layer 2. The second p-type impurity concentration distribution may not reach the pn junction part.
In the above-described Zener diode of the present embodiment, the concentration at the pn junction part is defined by the p-type semiconductor layer 3 in the anode region, which has low concentration and deep diffusion depth. Accordingly, even in the case where the impurity layers are formed by low-temperature thermal treatment for the purpose of element size miniaturization, the pn junction part, on which leakage current concentrates, can have low impurity concentration (specifically, 1×1018 to 5×1018 cm−3) compared with a conventional one, resulting in a reduction in leakage current. Further, the p-type semiconductor layer 4 having a peak concentration of approximately 3×1019 to 1×1020 cm−3 is formed in the vicinity of the substrate surface in the anode region, so that the resistance of the anode region is lowered and an increase in contact resistance between the anode region and the electrode can be suppressed.
A semiconductor device manufacturing method according to Embodiment 1 will be described below with reference to
First, as shown in
Next, as shown in
Subsequently, after the resist films 14a and 14b are removed, the semiconductor substrate 11 is subjected to thermal treatment at a temperature of, for example, approximately 1000° C. for approximately 20 to 30 minutes in an atmosphere of, for example, N2 to diffuse the implanted n-type impurity 13 and the implanted p-type impurity 15, thereby forming an n-type impurity layer 16 and a p-type impurity layer 17, as shown in
Thereafter, as shown in
Next, as shown in
Subsequently, as shown in
Thereafter, as shown in
The Zener diode manufacturing method of the present embodiment as described above attains a Zener diode having the same structure as that in the present embodiment shown in
In the Zener diode manufacturing method of the present embodiment, the p-type impurity layer 20b is formed so as to have deep diffusion depth and low impurity concentration, thereby forming the low-concentration pn junction part, on which leakage current concentrates, reducing leakage current. Further, the formation of the p-type impurity layer 20a having shallow diffusion depth and high concentration in the vicinity of the substrate surface in the anode region lowers both the resistance of the anode region and the contact resistance between the anode region and the electrode.
A semiconductor device and a method for manufacturing it according to Embodiment 2 of the present invention will be described below with reference to the accompanying drawings.
As shown in
An n+ source region 103a and an n+ drain region 103b are formed in the surface portion in the n-channel field effect transistor formation region of the semiconductor substrate 101. On the region between the n+ source region 103a and the n+ drain region 103b of the semiconductor substrate 101, a gate electrode 111a is arranged with a gate dielectric film 110a interposed. The respective side faces of the gate electrode 111a are covered with interlayer insulting films 108b and 108c. A source electrode wiring 105a electrically connected with the n+ source region 103a is formed on the n+ source region 103a, a gate electrode wiring 105b electrically connected with the gate electrode 111a is formed on the gate electrode 111a, and a drain electrode wiring 105c electrically connected with the n+ drain region 103b is formed on the n+ drain region 103b.
In the semiconductor substrate 101, an n-type semiconductor region 102 is formed which includes the p-channel field effect transistor formation region and the Zener diode formation region and has an impurity concentration of, for example, approximately 2×1016 cm−3.
A p+ source region 104a (a lower layer), a p+ source region 106a (an upper layer), a p+ drain region 104b (a lower layer), and p+ drain region 106b (an upper layer) are formed in the surface portion of the p-channel field effect transistor formation region in the n-type semiconductor region 102. A gate electrode 111b is arranged on the region between the p+ source regions 104a and 106a and the p+ drain regions 104b and 106b in the p-channel field effect transistor formation region in the n-type semiconductor region with a gate dielectric film 110b interposed. The respective side faces of the gate electrode 111b are covered with interlayer insulating films 108e and 108f. A source electrode wiring 105d electrically connected with the p+ source region 106a is formed on the p+ source region 106a, a gate electrode wiring 105e electrically connected with the gate electrode 111b is formed on the gate electrode 111b, and a drain electrode wiring 105f electrically connected with the p+ drain region 106b is formed on the p+ drain region 106b.
In the Zener diode formation region in the n-type semiconductor region 102, an n-type impurity layer 103c having impurity concentration higher than the n-type semiconductor region 102 is formed in a cathode region and a p-type impurity layer 104c (a lower layer) and a p-type impurity layer 106c (an upper layer) are formed in an anode region in the Zener diode formation region so as to form pn junction with the n-type impurity layer 103c. In the present embodiment, the n-type impurity layer 103c is formed in the same step as the step of forming the n+ source region 103a and the n+ drain region 103b of the n-channel filed effect transistor. The p-type impurity layer 104c is formed in the same step as the step of forming the p+ source region 104a and the p+ drain region 104b of the p-channel filed effect transistor. As well, the p-type impurity layer 106c is formed in the same step as the step of forming the p+ source region 106a and the p+ drain region 106b of the p-channel filed effect transistor. An interlayer insulting film 108h is formed so as to cover a junction part (the pn junction) of the n-type impurity layer 103c and the p-type impurity layers 104c and 106c. A cathode electrode wiring 105g electrically connected with the n-type impurity layer 103c is formed on a part of the n-type impurity layer 103c where the interlayer insulting film 108h is not formed. An anode electrode wiring 105h electrically connected with the p-type impurity layer 106c is formed on a part of the p-type impurity layer 106c where the interlayer insulating film 108h is not formed. Accordingly, the pn junction part is located between the cathode electrode wiring 105g and the anode electrode wiring 105h.
In the present embodiment, each n-type impurity concentration distribution of the n+ source region 103a and the n+ drain region 103b of the n-channel field effect transistor and the n-type impurity layer 103c of the Zener diode is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 1×1020 to 5×1020 cm−1 and of which diffusion depth is approximately 0.3 to 0.5 μm, for example. Each p-type impurity concentration distribution of the p+ source region 104a and the p+ drain region 104b of the p-channel field effect transistor and the p-type impurity layer 104c of the Zener diode is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 7×1018 to 3×1019 cm−3 and of which diffusion depth is approximately 0.6 to 0.9 μm, for example. Each p-type impurity concentration distribution of the p+ source region 106a and the p+ drain region 106b of the p-channel field effect transistor and the p-type impurity layer 106c of the Zener diode is defined dominantly by a concentration profile of which peak concentration at the substrate surface portion is approximately 3×1019 to 1×1020 cm−3 and of which diffusion depth is approximately 0.3 to 0.5 μm, for example. In the Zener diode, the n-type impurity concentration distribution of the n-type impurity layer 103c and the p-type impurity concentration distributions of the p-type impurity layers 104c and 106c overlap with each other in the range of approximately 1 to 2 μm in the horizontal direction. Further, the impurity concentration at the pn junction part of the n-type impurity layer 103c and the p-type impurity layers 104c and 106c (where the n-type impurity concentration is balance with the p-type impurity concentration) is approximately 1×1018 to 5×1018 cm−3, for example.
In the present embodiment, the interlayer insulating films 108a to 108i are formed of BPSG films having a thickness of approximately 100 nm to 2 μm, for example. The cathode electrode wiring 105g and the anode electrode wiring 105h are made of Al—Si—Cu alloy of which main component is Al, for example. The source electrode wiring 105a, the gate electrode wiring 105b, the drain electrode wiring 105c, the source electrode wiring 105d, the gate electrode wiring 105e, and the drain electrode wiring 105f are made of Al—Si—Cu alloy similar to the cathode electrode wiring 105g and the anode electrode wiring 105h.
The first feature of the present embodiment lies in that in the Zener diode, the p-type semiconductor region (the anode region) formed of the p-type impurity layer 104c and the p-type impurity layer 106c has an impurity concentration distribution which is a combination of a first p-type impurity concentration distribution (defining the impurity concentration distribution of the p-type impurity layer 104c) having first diffusion depth and first peak concentration and a second p-type impurity concentration distribution (defining the impurity concentration distribution of the p-type impurity layer 106c) having second diffusion depth shallower than the first diffusion depth and second peak concentration higher than the first peak concentration. Wherein, the first p-type impurity concentration distribution is higher than the second p-type impurity concentration distribution in the concentration at the pn junction part.
In the present embodiment, the region where the concentration of the first p-type impurity concentration distribution is higher than the concentration of the second p-type impurity concentration distribution serves as the p-type impurity layer 104c while the region where the concentration of the second p-type impurity concentration distribution is higher than the concentration of the first p-type impurity concentration distribution serves as the p-type impurity layer 106c. In this case, the pn junction part is a junction part of the low-concentration p-type impurity layer 104c and the n-type impurity layer 103c. The second p-type impurity concentration distribution may not reach the pn junction part.
The second feature of the present embodiment lines in that the n-type impurity layer 103c of the Zener diode is formed in the same step as the step of forming the n+ source region 103a and the n+ drain region 103b of the n-channel field effect transistor, the p-type impurity layer 104c of the Zener diode is formed in the same step as the step of forming the p+ source region 104a and the p+ drain region 104b of the p-channel field effect transistor, and the p-type impurity layer 106c of the Zener diode is formed in the same step as the step of forming the p+ source region 106a and the p+ drain region 106b of the p-channel field effect transistor.
In the semiconductor integrated circuit as described above in the present embodiment, the concentration at the pn junction part of the Zener diode is defined by the p-type impurity layer 104c in the anode region, which has low concentration and deep diffusion depth. Accordingly, even in the case where the impurity layers are formed by low-temperature thermal treatment for the purpose of element size miniaturizing, the pn junction part, on which leakage current concentrates, can have low impurity concentration (specifically, approximately 1×1018 to 5×1018 cm−3) compared with a conventional one, resulting in a reduction in leakage current of the Zener diode. This prevents an increase in concentration at the pn junction part by low-temperature thermal treatment, resulting in implementation of further element size miniaturization with the impurity diffusion restrained. Further, the impurity layers in the cathode region and the anode region of the Zener diode are formed in the same step as the step of forming the impurity layers in the source regions and the drain regions of the CMOS circuit, enabling hybridization with the Zener diode and suppression of an increase in number of manufacturing steps.
A semiconductor device manufacturing method according to Embodiment 2 will be described below with reference to
First, as shown in
Next, as shown in
Subsequently, as shown in
Thereafter, after the SiO2 film pattern 152 on the substrate surface is removed, an Si3N4 film (not shown in the drawings) is deposited on the semiconductor substrate 150 and a resist film (not shown in the drawings) for covering a predetermined region of the Si3N4 film is formed and patterned on the Si3N4 film. Then, the Si3N4 film is etched using the resist film as a mask, element isolation insulating films 155a to 155d formed of, for example, SiO2 films are formed using the patterned Si3N4 film as a mask, as shown in
Next, after an insulating film to be a gate dielectric film and a conductive film (a polysilicon film, for example) to be a gate electrode are deposited on the semiconductor substrate 150, a resist film (not shown in the drawings) for covering a gate electrode formation region is formed and patterned on the polysilicon film and the insulating film and the polysilicon film are etched using the resist film as a mask. Thus, as shown in
Subsequently, as shown in
Thereafter, after the resist films 158a to 158c are removed, resist films 160a to 160c of which parts are opened correspondingly to the p-channel filed effect transistor formation region and an anode region of the Zener diode formation region are formed on the semiconductor substrate 150, as shown in
Next, after the resist films 160a to 160c are removed, the semiconductor substrate 150 is subjected to thermal treatment at a temperature of, for example, approximately 1000° C. for approximately 20 to 30 minutes in an atmosphere of, for example, N2 to diffuse the implanted n-type impurity 159a to 159c and the implanted p-type impurity 161a to 161c. Thus, n-type impurity layers 165a to 165c are formed in the source region and the drain region of the n-channel field effect transistor and the cathode region of the Zener diode, respectively, while p-type impurity layers 166a to 166c are formed in the source region and the drain region of the p-channel field effect transistor and the anode region of the Zener diode, respectively, as shown in
Subsequently, as shown in
Thereafter, as shown in
Next, on the interlayer insulating film 164, a resist film (not shown in the drawings) is formed and patterned of which predetermined regions are opened (specifically, regions corresponding to: each contact region in contact with the source region, the gate electrode, and the drain region of the n-channel field effect transistor; each contact region in contact with the source region, the gate electrode, and the drain region of the p-channel field effect transistor; and each contact region in contact with the cathode region and the anode region of the Zener diode). Then, the interlayer insulating film 164 is etched using the resist film as a mask to form interlayer insulating films 168a, 168d, 168g, and 168i respectively for covering the element isolation insulating films 155a to 155d, interlayer insulating films 168b and 168c for covering the respective side faces of the gate electrode 157a, interlayer insulating films 168e and 168f for covering the respective side faces of the gate electrodes 157b, and an interlayer insulating film 168h for covering the pn junction part, as shown in
Subsequently, after an Al—Si—Cu alloy film of which main component is Al is deposited on the semiconductor substrate 150 and the interlayer insulating films 168a to 168i thereon, a resist film (not shown in the drawings) is formed and patterned on the alloy film for covering predetermined regions (specifically, regions corresponding to: each contact region in contact with the source region, the gate electrode, and the drain region of the n-channel field effect transistor; each contact region in contact with the source region, the gate electrode, and the drain region of the p-channel field effect transistor; and each contact region in contact with the cathode region and the anode region of the Zener diode). Then, the alloy film is etched using the resist film as a mask. Thus, as shown in
According to the semiconductor device manufacturing method in the present embodiment as described above, the same structure can be obtained as that of the semiconductor device of the present embodiment shown in
Further, in the semiconductor device manufacturing method in the present embodiment, the p-type impurity layer 104c (166c) having deep diffusion depth and low concentration in the anode region of the Zener diode is formed to allow the pn junction part, on which leakage current concentrates, to have low concentration, reducing leakage current of the Zener diode. This prevents an increase in concentration of the pn junction part by low-temperature thermal treatment, and hence, the p+ source region and the p+ drain region of the p-channel filed effect transistor can be formed by low-temperature thermal treatment, implementing further element size miniaturization with impurity diffusion restrained. Moreover, formation of the p-type impurity layer 106c (167c) having shallow diffusion depth and high concentration at a vicinity of the substrate surface in the anode region of the Zener diode lowers both the resistance of the anode region and the contact resistance between the anode region and the electrode. In addition, the impurity layers in the cathode region and the anode region of the Zener diode are formed in the same step as the step of forming the impurity layers in the source regions and the drain regions of the CMOS circuit, enabling hybridization of the Zener diode with the CMOS circuit and preventing an increase in number of manufacturing steps.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-179672 | Jun 2005 | JP | national |
