Claims
- 1. A manufacturing process of a semiconductor device comprising the steps of:applying a first insulating film to a principal plane of a semiconductor substrate; forming a conductive section having a contact portion on said first insulating film; applying a second insulating film to said conductive section; applying a silicon nitride film to said first and second insulating films; removing a portion of said silicon nitride film leaving a remainder thereof extending over a predetermined portion of the principal plane of said semiconductor substrate; covering an exposed portion of the first and second insulating films and the remainder of the silicon nitride film with a third insulating film; forming a conductive path through said remainder of the silicon nitride film and said first insulating film to a principal plane of said semiconductor substrate; and forming a conductive path through said third insulating film to the contact portion of said conductive section.
- 2. A manufacturing process of a semiconductor device comprising the steps of:applying a first insulating film to a principal plane of a semiconductor substrate; forming a conductive section having upper and lower opposing surfaces and a contact portion, wherein the lower surface extends along and is in contact with the first insulating film; forming an oxide second insulating film contacting and covering the upper surface of the conductive section; applying a silicon nitride film to said first and second insulating films; removing said silicon nitride film at least from a region above the contact portion of said conductive section and the remaining silicon nitride film is on the side surfaces of said conductive section to selectively expose the surface of the first insulating film; covering the selectively exposed surface of said first insulating film and a remaining portion of the silicon nitride film with a third insulating film; and forming a conductive path through said third insulating film to the contact portion of said conductive section.
- 3. A manufacturing process of a semiconductor device comprising the steps of:applying an insulating film to a principal plane of a semiconductor substrate having a plurality of first contact portions; forming a conductive section having a second contact portion on said insulating film, wherein said conductive section has a top surface and a side surface; covering said insulating film and said conductive section with a silicon nitride film; removing said silicon nitride film from said insulating film, and the remaining said silicon nitride film covering only the top surface and the side surface of said conductive section; covering said silicon nitride film and said insulating film with another insulating film; forming a conductive path through said another insulating film and said silicon nitride film to the second contact portion of said conductive section; and forming a second conductive path through said insulating film and said another insulating film to one of the plurality of first contact portions of said semiconductor substrate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-11624 |
Jan 1996 |
JP |
|
Parent Case Info
This application is a Continuation of application Ser. No. 09/283,752 filed Apr. 2, 1999, now U.S. Pat. No. 6,268,278 which is a Divisional of application Ser. No. 08/687,624 filed on Jul. 26, 1996 and now U.S. Pat. No. 6,087,710.
US Referenced Citations (26)
Foreign Referenced Citations (8)
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Country |
43 37 355 |
May 1995 |
DE |
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Mar 1993 |
EP |
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May 1992 |
JP |
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Aug 1993 |
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JP |
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JP |
5-343636 |
Dec 1993 |
JP |
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Non-Patent Literature Citations (2)
Entry |
T. Ema et al., “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS”, IEEE, 1988, pp. 592-595. |
K.H. Kusters et al., “A High Density 4Mbit dRAM Process Using a Fully Overlapping Bitline Contact (FOBIC) Trench Cell”, pp. 93-94. |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/283752 |
Apr 1999 |
US |
Child |
09/760641 |
|
US |