Patent Application
20240413017
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of using hard mask to protect fin-shaped structures on low-voltage (LV) region while a thermal treatment process is conducted on the medium-voltage (MV) region for forming gate dielectric layer.
In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance.
Moreover with the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
However as the scale of current devices continue to decrease the integration of high-voltage devices and FinFET devices start to face numerous challenges such as current leakage and control of breakdown voltage. Hence, how to improve the current fabrication for improving performance of the device has become an important task in this field.
According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of providing a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, forming fin-shaped structures on the LV region, forming an insulating layer between the fin-shaped structures, forming a hard mask on the LV region, and then performing a thermal oxidation process to form a gate dielectric layer on the MV region. Preferably, a hump is formed on the substrate surface of the MV region after the hard mask is removed, in which the hump further includes a first hump adjacent to one side of the substrate on the MV region and a second hump adjacent to another side of the substrate on the MV region.
According to another aspect of the present invention, a semiconductor device includes a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, a first hump on the substrate of the MV region, and a gate electrode on the first hump. Preferably, the hump includes a first ring-shape under a top view perspective.
According to yet another aspect of the present invention, a semiconductor device includes a substrate having a medium-voltage (MV) region and a low-voltage (LV) region, a first hump on one side of the substrate of the MV region, a second hump on another side of the substrate of the MV region, and a gate electrode on the first hump and the second hump.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
In this embodiment, the regions 16, 18 could be transistor regions having same conductive type or different conductive types. For instance, each of the two regions 16, 18 could be a PMOS region or a NMOS region and the regions 16, 18 are defined to fabricate gate structures having different threshold voltages in the later process. Preferably, it would be desirable to first conduct an implantation process to form p-type deep wells on the MV region 16 and a n-type deep well on the LV region 18, but not limited thereto.
Next, a base 22 is formed on the MV region 16 and a plurality of fin-shaped structures 24 are formed on the substrate 12 of the LV region 18. Preferably, the fin-shaped structures 24 could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained.
Alternatively, the base 22 and the fin-shaped structures 24 could also be obtained by first forming a patterned mask (not shown) on the substrate, 12, and through an etching process, the pattern of the patterned mask is transferred to the substrate 12 to form the base 22 and the fin-shaped structures 24. Moreover, the formation of the base 22 and the fin-shaped structures 24 could also be accomplished by first forming a patterned hard mask (not shown) on the substrate 12, and a semiconductor layer composed of silicon germanium is grown from the substrate 12 through exposed patterned hard mask via selective epitaxial growth process to form the corresponding the base 22 and fin-shaped structures 24. These approaches for forming the base 22 and fin-shaped structures 24 are all within the scope of the present invention.
In this embodiment, a pad layer 26 made of silicon oxide (SiO2) and a pad layer (not shown) made of silicon nitride (SiN) could be formed on each of the base 22 and the fin-shaped structures 24 during the aforementioned patterning process. In this MV region 16, the pad layer 26 preferably covers the surface of the entire active area 62.
Next, as shown in
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Next, as shown in
Next, as shown in
Since the central portion of the substrate 12 on the MV region 16 is reacted first to form the gate dielectric layer 34 made of SiO2 while peripheral or edge portion of the substrate 12 is reacted afterwards, the overall process of conducting the RTO process 42 for oxidizing the surface of the substrate 12 on MV region 16 preferably forms a hump 36 on the substrate 12 surface. Preferably, the hump 36 is formed by the elevated edge or peripheral portion of the substrate 12 hence the hump 36 and the substrate 12 are made of same material.
It should be noted that since the gate dielectric layer 34 is formed along with the hump 36 on the substrate 12 surface, the top surface of the gate dielectric layer 34 on two adjacent sides also forms another hump 46. Similarly, since the hump 46 is formed by the edge portion of the gate dielectric layer 34, the hump 46 and the gate dielectric layer 34 are made of same material.
Referring to
Similarly, the hump 46 on the surface of the gate dielectric layer 34 on MV region 16 could further include a hump 48 adjacent to one side such as left of the gate dielectric layer 34 and another hump 50 adjacent to another side such as right side of the gate structure layer 34, in which the top surface of each of the humps 48, 50 could be an inclined planar surface, a curved surface, an L-shape surface, or a V-shape surface, which are all within the scope of the present invention. From a top view perspective, the hump 36 on the active area 62 surface of the substrate 12 includes a ring shape that surrounds the four corners of the active area 62. Similarly, the hump 46 on the gate dielectric layer 34 surface also includes a ring that surrounds the four corners of the active area 62, in which the ring formed by the hump 46 on the gate dielectric layer 34 surface could completely overlap or partially overlap the ring formed by the hump 36 on the substrate 12 surface underneath. In other words, the area of the ring formed by the hump 46 on gate dielectric layer 34 surface could be greater than, equal to, or less than the area of the ring formed by the hump 36 on substrate 12 surface underneath, which are all within the scope of the present invention.
Referring to
Next, a standard metal-oxide semiconductor (MOS) transistor fabrication process could be carried out by forming elements such as source/drain regions 58 in the substrate 12 adjacent to two sides of the gate electrodes 54, 56. Since the fabrication of a standard MOS transistor process is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity. Viewing from a top view of
Overall, the present invention first forms a STI around the substrate on the MV region and fin-shaped structures on the LV region, forms a hard mask made of SiN on both MV region and LV region, removes the hard mask on the MV region, and then conducts a RTO process 42 to form a gate dielectric layer on the substrate surface of the MV region. Since the fin-shaped structures on the LV region is covered with hard mask 32 during the RTO process 42, the high temperature used during the RTO process 42 would not affect the density of the fin-shaped structures to result in fin width shrinkage and performance of the transistors would be preserved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 112121791 | Jun 2023 | TW | national |
