Patent Application
20230096911
The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2021-0127975, filed on Sep. 28, 2021 in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
Exemplary embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device including a capacitor and a method for fabricating the semiconductor device.
Recently, as design rules continue to decrease, semiconductor devices have been developed with greater capacity and a higher degree of integration. These trends are also seen in Dynamic random-access memory (DRAM) devices. In order for a DRAM device to operate, memory cells must have capacitance of a minimum predetermined level or higher.
Embodiments of the present invention are directed to a semiconductor device including a capacitor, and a method for fabricating the semiconductor device.
In accordance with an embodiment of the present disclosure, a capacitor includes: a bottom electrode; a top electrode; and a hybrid dielectric layer including at least one nanosheet material disposed between the bottom electrode and the top electrode.
In accordance with another embodiment of the present disclosure, a semiconductor device includes: a transistor including a first source/drain region, a second source/drain region, and a channel between the first source/drain region and a second source/drain region; a word line positioned over the channel of the transistor; a bit line coupled to the first source/drain region of the transistor; and a capacitor coupled to the second source/drain region of the transistor, wherein the capacitor includes: a bottom electrode coupled to the second source/drain region; a top electrode; and a hybrid dielectric layer including at least one nanosheet material disposed between the bottom electrode and the top electrode.
Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where one or more other exists between the first layer and the second layer or the substrate.
A paraelectric material may include HfO2, ZrO2, TiO2, or a combination thereof. However, the paraelectric material has limitations in reducing the effective oxide thickness (Tox) due to its low dielectric constant (k<60) of less than approximately 60.
A material having a higher dielectric constant than the paraelectric material, that is, a super high-k material, has been proposed for use in memory devices. The super high-k material may include a bulk perovskite material, as an example. The bulk perovskite material may include BaTiO3, PZT, or the like. However, in applications, the bulk perovskite material can present problems because the dielectric constant decreases rapidly at thin thicknesses.
A capacitor of a highly integrated DRAM may require a super high-k material having an effective oxide thickness (Tox) of approximately two angstroms (2 Å) or less and a dielectric constant of approximately 60 or more at a thickness of approximately five nanometers (5 nm) or less.
A negative capacitor has been proposed for capacitance boosting. A hybrid dielectric layer of a negative capacitor may include a stack of a ferroelectric material and a paraelectric material. However, the capacitance may drop sharply due to inter-mixing of atoms between the electrodes in the memory device and the hybrid dielectric layer. For example, the negative capacitance may drop sharply due to inter-mixing of atoms between the electrodes and a ferroelectric material, between the electrodes and a paraelectric material, and between the paraelectric material and the ferroelectric material.
The embodiments described below relate to a negative capacitor that may include a hybrid dielectric layer having a negative capacitance.
The hybrid dielectric layer may include a stack with a nanosheet material and a ferroelectric material. The nanosheet material may be a two-dimensional oxide nanosheet, and may have a thickness of approximately 0.4 to 2 nanometers (nm). The nanosheet material may have a super high-k material of approximately 200 or greater. The nanosheet material may be selected so that the dielectric constant of the nanosheet does not decrease with a decrease in sheet thickness. The nanosheet material may have a clean interface.
The nanosheet material may include a super high-k material including titanium (Ti), niobium (Nb), calcium (Ca), strontium (Sr), tantalum (Ta), europium (Eu), lanthanum (La), and combinations thereof. For example, the nanosheet material may include Ti0.87O2, Ti0.91O2, Nb3O8, TiNbO5, Ti2NbO7, Ti5NbO14, Ca2Nb3O10, Ca3Nb4O13, Ca4Nb5O16, Sr2Nb3O10, Sr3Nb4O13, Sr4Nb5O16, Ca2Ta3O10, Ca3Ta4O13, Ca4Ta5O16, Sr2Ta3O10, Sr3Ta4O13, Sr4Ta5O16, Eu0.53Ta2O7, or LaNb2O7. The nanosheet material may be crystalline.
The ferroelectric material may include a perovskite-based material. For example, the ferroelectric material FE may include Hf1-xZrxO2 (0<x<1), doped Hf1-xZrxO2 (dopant: La, Si, Y, Al), Ba1-xSrxTiO3 (0<x<1), PbTiO3, PbZr1-xTixO3 (0<x<1), BiFeO3, or a combination thereof.
A method for forming a nanosheet material may include coating a polymer material having a positive charge, depositing an inorganic nanosheet having a negative charge, and removing the polymer material by performing an super violet ray (UV) treatment. The polymer material may include PDDA or PEI. Deposition of the inorganic nanosheet may include a layer-by-layer deposition (LBL) deposition method.
The ferroelectric material may be deposited by Atomic Layer Deposition (ALD).
A dielectric layer including the nanosheet material may prevent intermixing between the ferroelectric material and the nanosheet material.
The dielectric layer including the nanosheet material may prevent the formation of an amorphous layer having a low dielectric constant between the top and bottom electrodes and the dielectric layer in a subsequent high-temperature heat treatment and may prevent deterioration of the negative capacitance.
Referring to
The bottom electrode BE and the top electrode TE may include a conductive material. The bottom electrode BE and the top electrode TE may each include a semiconductor material, a metal, a metal oxide, a metal nitride, or a combination thereof. For example, the bottom electrode BE and the top electrode TE may include polysilicon, silicon germanium, TiN, TaN, Pt, Au, Pd, Ni, Mo, W, WN, Ru, RuO, Nb doped SrTiO3, SrRuO3 or a combination thereof.
The hybrid dielectric layer DE may include at least one nanosheet material and at least one ferroelectric material. According to embodiments of the present disclosure, the hybrid dielectric layer DE may include a first nanosheet material NS1, a ferroelectric material FE, and a second nanosheet material NS2. The ferroelectric material FE may be disposed between the first and second nanosheet materials NS1 and NS2. Each of the first and second nanosheet materials NS1 and NS2 may include a paraelectric material. Each of the first and second nanosheet materials NS1 and NS2 may include a two-dimensional inorganic material. Each of the first and second nanosheet materials NS1 and NS2 may include a super high-k material including titanium (Ti), niobium (Nb), calcium (Ca), strontium (Sr), tantalum (Ta), europium (Eu), lanthanum (La) or a combination thereof. For example, each of the first and second nanosheet materials NS1 and NS2 may include Ti0.87O2, Ti0.91O2, Nb3O8, TiNbO5, Ti2NbO7, Ti5NbO14, Ca2Nb3O10, Ca3Nb4O13, Ca4Nb5O16, Sr2Nb3O10, Sr3Nb4O13, Sr4Nb5O16, Ca2Ta3O10, Ca3Ta4O13, Ca4Ta5O16, Sr2Ta3O10, Sr3Ta4O13, Sr4Ta5O16, Eu0.53Ta2O7, or LaNb2O7.
The ferroelectric material FE may include a perovskite-based material. For example, the ferroelectric material FE may include Hf1-xZrxO2 (0<x<1), doped Hf1-xZrxO2 (dopant: La, Si, Y, Al), Ba1-xSrxTiO3 (0<x<1), PbTiO3, PbZr1-xTixO3 (0<x<1), or BiFeO3.
According to another embodiment of the present disclosure, in the hybrid dielectric layer DE, the second nanosheet material NS2 may be omitted. In other words, the hybrid dielectric layer DE may include a stack of the first nanosheet material NS1 and the ferroelectric material FE.
According to other embodiments of the present disclosure, in the hybrid dielectric layer DE, either the first nanosheet material NS2 or the second nanosheet material NS1 may be omitted.
Referring to
In
In
Referring to
In
Referring again to
Referring to
The substrate 101 may include a material appropriate for semiconductor processing. For example, the substrate 101 may include a semiconductor substrate, and the semiconductor substrate may be formed of a material containing silicon. The semiconductor substrate may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multi-layers thereof. The semiconductor substrate may also include other semiconductor materials, such as germanium. The semiconductor substrate may include a III/V-group semiconductor substrate, for example, a compound semiconductor substrate, such as GaAs. The semiconductor substrate may include a Silicon-On-Insulator (SOI) substrate.
Bottom portions of the bottom electrodes 105 may penetrate an etch stop layer 104, which may be located on the inter-layer dielectric layer 102, to be coupled to the contact plugs 103. The bottom electrodes 105 may have a cylinder shape. The outer walls of the bottom electrodes 105 may be supported by the supporters 106 and 107. In
The bottom electrodes 105 may have a cylinder shape. The bottom electrodes 105 may include a semiconductor material or a metal-based material. The metal-based material may include a metal, a metal nitride, a metal silicon nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof. For example, the bottom electrodes 105 may include polysilicon, silicon germanium, TiN, TaN, Pt, Au, Pd, Ni, Mo, W, WN, Ru, RuO, Nb-doped SrTiO3, SrRuO3, or a combination thereof.
The hybrid dielectric layer 108 may be disposed between the bottom electrode 105 and the top electrode 109. The hybrid dielectric layer may include a high-k material having a higher dielectric constant than silicon oxide and silicon nitride. The hybrid dielectric layer 108 may include a first nanosheet material NS1, a ferroelectric material FE, and a second nanosheet material NS2. The ferroelectric material FE may be sandwiched between the first nanosheet material NS1 and the second nanosheet material NS2. Each of the first and second nanosheet materials NS1 and NS2 may include a paraelectric material. The first and second nanosheet materials NS1 and NS2 may each include a two-dimensional inorganic material. Each of the first and second nanosheet materials NS1 and NS2 may include a super high-k material including titanium (Ti), niobium (Nb), calcium (Ca), strontium (Sr), tantalum (Ta), europium (Eu), lanthanum (La) or a combination thereof. For example, the first and second nanosheet materials NS1 and NS2 may each include Ti0.87O2, Ti0.91O2, Nb3O8, TiNbO5, Ti2NbO7, Ti5NbO14, Ca2Nb3O10, Ca3Nb4O13, Ca4Nb5O16, Sr2Nb3O10, Sr3Nb4O13, Sr4Nb5O16, Ca2Ta3O10, Ca3Ta4O13, Ca4Ta5O16, Sr2Ta3O10, Sr3Ta4O13, Sr4Ta5O16, Eu0.53Ta2O7, or LaNb2O7. The ferroelectric material FE may include a perovskite-based material. For example, ferroelectric material FE may include Hf1-xZrxO2 (0<x<1), doped Hf1-xZrxO2 (dopant: La, Si, Y, Al), Ba1-xSrxTiO3 (0<x<1), PbTiO3, PbZr1-xTixO3 (0<x<1), or BiFeO3.
The top electrode 109 may include a semiconductor material or a metal-based material. The metal-based material may include a metal, a metal nitride, a metal silicon nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof. For example, the bottom electrodes 105 may include polysilicon, silicon germanium, TiN, TaN, Pt, Au, Pd, Ni, Mo, W, WN, Ru, RuO, Nb-doped SrTiO3, SrRuO3, or a combination thereof.
Referring to
Contact plugs 13 may be formed in the inter-layer dielectric layer 12. The contact plugs 13 may penetrate the inter-layer dielectric layer 12 to be electrically connected to a portion of the substrate 11. The contact plugs 13 may include a semiconductor material, such as a metal, a metal nitride, a metal silicide, or a combination thereof. For example, the contact plugs 13 may include polysilicon, tungsten, tungsten nitride, titanium nitride, titanium silicon nitride, titanium silicide, cobalt silicide, or a combination thereof. According to another embodiment of the present disclosure, the contact plugs 13 may be stacked in the order of a semiconductor material, a metal silicide, a metal nitride, and a metal. The contact plugs 13 may be spaced apart from each other in a lateral direction.
Although not illustrated, a plurality of word lines and bit lines may be formed over the substrate 11, in the substrate 11, or both. The inter-layer dielectric layer 12 may be formed to cover the word lines and the bit lines. Impurity regions (not shown) may be formed in the substrate 11 on both sides of each of the word lines, and each of the contact plugs 13 may be coupled to one from among the impurity regions.
An etch stop layer 14 may be formed over the inter-layer dielectric layer 12 and the contact plugs 13, and a mold structure ML may be formed over the etch stop layer 14. The etch stop layer 14 may include silicon nitride. The mold structure ML may be a stack structure including different dielectric materials. For example, the mold structure ML may be stacked on the etch stop layer 14 in the order of a first mold layer 15, a first support layer 16, a second mold layer 17, and a second support layer 18. The first support layer 16 and the second support layer 18 may include a material having an etch selectivity with respect to the first and second mold layers 15 and 17. The first support layer 16 and the second support layer 18 may include a silicon nitride-based material. For example, when the first mold layer 15 and the second mold layer 17 includes silicon oxide, and the first support layer 16 and the second support layer 18 may include silicon nitride. According to other embodiments of the present disclosure, the first support layer 16 and the second support layer 18 may include silicon carbon nitride or silicon boron nitride. According to further embodiments of the present disclosure, each of the first support layer 16 and the second support layer 18 may include a stack of silicon nitride and silicon carbon nitride or a stack of silicon nitride and silicon boron nitride.
Referring to
Subsequently, the etch stop layer 14 may be etched to expose the upper surface of each of the contact plugs 13 below the openings 19.
The openings 19 may be formed by a double patterning process. For example, the mask layer for forming the openings 19 may have a mesh-shape which is formed by combining a spacer patterning technique that is performed twice.
Referring to
Referring to
From the perspective of a top view, the upper-level supporter opening 21 may have a shape that partially exposes the outer walls of the three neighboring bottom electrodes 20. According to another embodiment of the present disclosure, the upper-level supporter opening 21 may have a shape that partially exposes the outer walls of at least four or more bottom electrodes 20. The cross section of the upper-level supporter opening 21 may have a triangular, quadrangular, parallelogram, pentagonal, hexagonal or honeycomb shape.
By the upper-level supporter opening 21, the outer walls of all the bottom electrodes 20 may be partially exposed. This may be referred to as an ‘all open bottom electrode array’.
According to another embodiment of the present disclosure, the upper outer wall of the at least one bottom electrode 20 may not be exposed due to the upper-level supporter opening 21. For example, among the bottom electrodes 20, there may be at least one bottom electrode 20 that is not exposed by the upper-level supporter opening 21 but fully covered by the upper-level supporter 18S. This may be referred to as a ‘1-span bottom electrode array’.
Referring to
After the second mold layer 17 is removed, the first support layer 16 under opening 21 may be removed, and the remaining portions of first support layer 16 may be etched to form the lower-level supporter 16S. The lower-level supporter 16S may contact the outer walls of the bottom electrodes 20. Some surfaces of the first mold layer 15 may be exposed by the lower-level supporter 16S. The lower-level supporter 16S may have a shape that partially surrounds the outer walls of the bottom electrodes 20. The lower-level supporter 16S may prevent the bottom electrodes 20 from collapsing in the subsequent process of removing the first mold layer 15. The lower-level supporter 16S and the upper-level supporter 18S may have the substantially the same cross-sectional shape.
Subsequently, the first mold layer 15 may be removed. The first mold layer 15 may be removed by a wet dip-out process. The first mold layer 15 may be selectively removed, and thus the surface of the etch stop layer 14 may be exposed. The wet dip-out process for removing the first mold layer 15 may be performed using an etching solution capable of selectively removing the first mold layer 15. When the first mold layer 15 includes silicon oxide, the first mold layer 15 may be removed by a wet etching process using hydrofluoric acid (HF).
A lower-level supporter 16S and an upper-level supporter 18S supporting the outer walls of the bottom electrodes 20 may be formed by a series of processes as described above with reference to
Referring to
The hybrid dielectric layer 21 may include a first nanosheet material NS1, a ferroelectric material FE, and a second nanosheet material NS2. The first and second nanosheet materials NS1 and NS2 may each include a paraelectric material. Each of the first and second nanosheet materials NS1 and NS2 may include a two-dimensional inorganic material. The first and second nanosheet materials NS1 and NS2 may each include a super high-k material including titanium (Ti), niobium (Nb), calcium (Ca), strontium (Sr), tantalum (Ta), europium (Eu), lanthanum (La) or a combination thereof. For example, the first and second nanosheet materials NS1 and NS2 may include Ti0.87O2, Ti0.91O2, Nb3O8, TiNbO5, Ti2NbO7, Ti5NbO14, Ca2Nb3O10, Ca3Nb4O13, Ca4Nb5O16, Sr2Nb3O10, Sr3Nb4O13, Sr4Nb5O16, Ca2Ta3O10, Ca3Ta4O13, Ca4Ta5O16, Sr2Ta3O10, Sr3Ta4O13, Sr4Ta5O16, Eu0.53Ta2O7, or LaNb2O7.
The ferroelectric material FE may include a perovskite-based material. For example, the ferroelectric material FE may include Hf1-xZrxO2 (0<x<1), doped Hf1-xZrxO2 (dopant: La, Si, Y, Al), Ba1-xSrxTiO3 (0<x<1), PbTiO3, PbZr1-xTixO3 (0<x<1), or BiFeO3.
The hybrid dielectric layer 21 may have a double-layer structure as illustrated in
Referring to
Referring to
The hybrid dielectric layer 108 of
Referring to
The hybrid dielectric layer 108 of
Referring to
The bit line BL may be vertically oriented in the first direction D1. The bit line BL may be referred to as a vertically oriented bit line or a pillar-type bit line. The bit line BL may include a conductive material. The bit line BL may include a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The bit line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may include polysilicon or titanium nitride (TiN) which is doped with an N-type impurity. The bit line BL may include a stack (TiN/W) of titanium nitride and tungsten.
The double word line DWL may extend in the third direction D3, and the active layer ACT may extend in the second direction D2. The active layer ACT may be arranged laterally from the bit line BL. The double word line DWL may include a first word line WL1 and a second word line WL2. The first word line WL1 and the second word line WL2 may be spaced apart in the first direction D1 with the active layer ACT interposed therebetween. A gate dielectric layer GD may be formed over the upper and lower surfaces of the active layer ACT.
The active layer ACT may include a semiconductor material. For example, the active layer ACT may include silicon, germanium, or silicon-germanium. The active layer ACT may include a channel CH, a first source/drain region SR between the channel CH and the bit line BL, and a second source/drain region DR between the channel CH and the capacitor CAP. According to another embodiment of the present disclosure, the active layer ACT may include an oxide semiconductor material. For example, the oxide semiconductor material may include Indium Gallium Zinc Oxide (IGZO). When the active layer ACT is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first and second source/drain regions SR and DR may be omitted. According to another embodiment of the present disclosure, the active layer ACT may include monocrystalline silicon, and thus the mobility of a transistor may be improved.
The first source/drain region SR and the second source/drain region DR may be doped with an impurity of the same conductivity type. For example, the first source/drain region SR and the second source/drain region DR may be doped with an N-type impurity or a P-type impurity. The first source/drain region SR and the second source/drain region DR may include at least one impurity selected among arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. A first side of the first source/drain region SR may be in contact with the bit line BL, and a second side of the first source/drain region SR may be in contact with the channel CH. A first side of the second source/drain region DR may be in contact with the storage node BE, and a second side of the second source/drain region DR may be in contact with the channel CH. The second side of the first source/drain region SR and the second side of the second source/drain region DR may partially overlap with the first and second word lines WL1 and WL2, respectively. The lateral length of the channel CH in the second direction D2 may be smaller than the lateral length of the first and second source/drain regions SR and DR in the second direction D2. According to another embodiment of the present disclosure, the lateral length of the channel CH in the second direction D2 may be greater than the lateral length of the first and second source/drain regions SR and DR in the second direction D2.
The transistor TR is a cell transistor and may have a double word line DWL. In the double word line DWL, a first word line WL1 and a second word line WL2 may have the same potential. The same word line driving voltage may be applied to the first word line WL1 and the second word line WL2. As such, the semiconductor device 400 in accordance with an embodiment of the present disclosure may have a double word line DWL in which two first and second word lines WL1 and WL2 are disposed adjacent to one channel CH.
The active layer ACT may have a thickness that is less than the thicknesses of the first and second word lines WL1 and WL2. In other words, a vertical thickness of the active layer ACT in the first direction D1 may be smaller than a vertical thickness of each of the first and second word lines WL1 and WL2 in the first direction D1.
As described above, a thin active layer ACT may be referred to as a thin-body active layer. The thin active layer ACT may include a thin channel CH. Hereinafter, the channel CH may be simply referred to as a ‘thin-body channel (CH)’.
The upper and lower surfaces of the active layer ACT may have a flat or substantial flat surface. In other words, the upper and lower surfaces of the active layer ACT may be parallel to each other in the second direction D2.
The gate dielectric layer GD may include silicon oxide, silicon nitride, a metal oxide, a metal oxynitride, a metal silicate, a high-k material, a ferroelectric material, an anti-ferroelectric material, or a combination thereof. The gate dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.
The first and second word lines WL1 and WL2 of the double word line DWL may include a metal, a metal mixture, a metal alloy, or a semiconductor material. The double word line DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the double word line DWL may include a TiN/W stack in which titanium nitride and tungsten are sequentially stacked. The double word line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function, which is lower than approximately 4.5 eV, and the P-type work function material may have a high work function, which is higher than approximately 4.5 eV.
According to an embodiment of the present disclosure, the double word line DWL may include a pair of two word lines, which include the first word line WL1 and the second word line WL2, with the active layer ACT interposed therebetween.
The capacitor CAP may be disposed laterally in the second direction D2 from the transistor TR. The capacitor CAP may include a storage node BE, which extends laterally from the active layer ACT in the second direction D2. The capacitor CAP may further include a hybrid dielectric layer DE and a plate node TE over the storage node BE. The storage node BE, the hybrid dielectric layer DE, and the plate node TE may be arranged laterally in the second direction D2. The storage node BE may have a laterally oriented pillar shape. The hybrid dielectric layer DE may conformally cover the outer wall of the storage node BE. The storage node BE may be electrically connected to the second source/drain region DR.
The storage node BE may have a three-dimensional (3D) structure, and the storage node BE having a three-dimensional structure may have a horizontal three-dimensional structure which is oriented in the second direction D2. As an example of the 3D structure, the storage node BE may have a pillar shape that extends in the second direction D2. According to another embodiment of the present disclosure, the storage node BE may have a cylindrical shape or a plate shape.
The hybrid dielectric layer DE may include a high-k material having a higher dielectric constant than silicon oxide and silicon nitride. The hybrid dielectric layer DE may include a first nanosheet material NS1, a ferroelectric material FE, and a second nanosheet material NS2. The first and second nanosheet materials NS1 and NS2 may include a paraelectric material. The first and second nanosheet materials NS1 and NS2 may include a 2D inorganic material. The first and second nanosheet materials NS1 and NS2 may include a super high-k material including titanium (Ti), niobium (Nb), calcium (Ca), strontium (Sr), tantalum (Ta), europium (Eu), lanthanum (La) or a combination thereof. For example, the first and second nanosheet materials NS1 and NS2 may include Ti0.87O2, Ti0.91O2, Nb3O8, TiNbO5, Ti2NbO7, Ti5NbO14, Ca2Nb3O10, Ca3Nb4O13, Ca4Nb5O16, Sr2Nb3O10, Sr3Nb4O13, Sr4Nb5O16, Ca2Ta3O10, Ca3Ta4O13, Ca4Ta5O16, Sr2Ta3O10, Sr3Ta4O13, Sr4Ta5O16, Eu0.53Ta2O7, or LaNb2O7. The ferroelectric material FE may include a perovskite-based material. For example, the ferroelectric material FE may include Hf1-xZrxO2 (0<x<1), doped Hf1-xZrxO2 (dopant: La, Si, Y, Al), Ba1-xSrxTiO3 (0<x<1), PbTiO3, PbZr1-xTixO3 (0<x<1), or BiFeO3. The hybrid dielectric layer DE may have a double layer structure as illustrated in
Referring to
Also, when an oxide semiconductor material is used as the thin body channel CH, on-current may be secured sufficiently due to low leakage characteristics. Thus, even if a plate capacitor with a small area is formed, the cell density of 3D DRAM may be increased.
Also, manufacturing process restrictions may be reduced because the capacitor forming process can be performed at a room temperature so to reduce deleterious effects on 3D DRAM cells.
According to an embodiment of the present disclosure, a capacitor having a high dielectric constant of approximately 200 or more may be formed by utilizing a hybrid dielectric layer including a nanosheet material.
According to an embodiment of the present disclosure, a capacitor having a negative capacitance may be formed by using a hybrid dielectric layer including a nanosheet material.
The desirable effects to be obtained in the embodiments of the present disclosure are not limited to those effects mentioned above. Other effects not mentioned above may also be clearly understood by those of ordinary skill in the art to which the present invention pertains from the description in the disclosure.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2021-0127975 | Sep 2021 | KR | national |
