Patent Application
20090212293
1. Field of the Invention
The invention relates in general to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device with two doped regions adjacent to the channel region and a method of fabricating the same.
2. Description of the Related Art
Recently, a part of the semiconductive circuits, such as the pixel circuit and the driving circuit, applied to the active-matrix display have been directly formed on the glass substrate. More semiconductive circuits, such as memory circuit and logic circuit, are also disposed on the glass substrate for reducing cost. Polysilicon transistor, which is characterized by high carrier mobility, is preferably applied to memory circuit or logic circuit which ought to be operated in high velocity. In general, the low temperature polysilicon (LTPS) technology is the main stream of methods for fabricating polysilicon transistor since the glass the circuits formed on it undergo lower temperature and less damage during fabricating process. Among LTPS technology, the metal induced crystallization (MIC) process is focused attention upon because it is characterized by high displaying uniformity, reduced number of compensating circuit used in pixel circuit, high yield, and high opening ratio. During the MIC process, the metal, so-called catalyst, is doped into the amorphous silicon to decrease the required temperature at which amorphous silicon is able to be transformed to polysilicon.
However, if the catalyst left in the polysilicon layer, the channel region composed of polysilicon and catalyst would be defected so as to cause leakage of current. Although the X V group elements or halogen have been added to the polysilicon layer other than the channel region for attracting the catalyst from the channel region, the catalyst, which remains at the channel region after this treatment, still results in defect of deep level and leakage of current so as to deteriorate the character of the transistor.
In view of the foregoing, it is an object of the present invention to provide a semiconductor device and a method of fabricating the same, which is capable of decreasing the crystallization promoting material in the channel region and improving the electric character of the semiconductor device.
The invention achieves the above-identified object by providing a semiconductor device, comprising a substrate, a semiconductive layer and a gate electrode. The semiconductive layer having a crystallization promoting material is formed over the substrate. The semiconductive layer has a channel region, a first doped region and a second doped region. The first doped region has a donor and an acceptor, and the second doped region has a dopant which is selected from one of the donor and the acceptor. The second doped region is disposed between the first doped region and the channel region. The gate electrode is insulated from the channel region.
It is another object of the invention to provide a method for fabricating a method of fabricating a semiconductor device, comprising (a) providing a substrate; (b) forming a semiconductive layer having a crystallization promoting material on the substrate; (c) forming a channel region, a first doped region, and a second doped region in the semiconductive layer, the second doped region positioned between the first doped region and the channel region, wherein the first doped region has two dopants including a donor and a acceptor, the second doped region has a dopant selected from one of the donor and the acceptor; (d) forming a gate electrode insulated from the channel region; and (e) recovering the semiconductor device with a heat treatment so as to allow the crystallization promoting material to be moved away from the channel region.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The semiconductor device of the invention comprises a substrate, a semiconductive layer, and a gate electrode. The semiconductive layer having a crystallization promoting material is formed over the substrate, and the semiconductive layer has a channel region, a first doped region, and a second doped region. The first doped region has a donor and an acceptor, and the second doped region has a dopant which is selected from one of the donor and the acceptor. The second doped region is disposed between the first doped region and the channel region. The gate electrode is insulated from the channel region.
The acceptor comprises at least one element selected from IIIA group elements, including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth(Bi). The donor comprises at least one element selected from VA group elements including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (TI). The crystallization promoting material is selected from iron (Fe), cobalt (Co), nickel (Ni), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), aurum (Au) or combination thereof to catalyze the transformation reaction from amorphous silicon to polysilicon.
Different types of the semiconductor device have corresponding kinds and concentration of the dopant doped in the first and second doped regions. If the semiconductor device is an N type transistor, the dopant of the second doped region is the donor, and a concentration of the donor in the first doped region is higher than a concentration of the acceptor in the first doped region. If the semiconductor device is a P type transistor, the dopant of the second doped region is the acceptor, and the concentration of the donor in the first doped region is lower than the concentration of the acceptor in the first doped region.
The crystallization promoting material is apt to be attracted by the acceptor. It is noted that the first doped region doped with both of the donor and the acceptor provides more attractiveness to the crystallization promoting material than one region doped with only acceptor. The first and second doped regions are capable of attracting the crystallization promoting material and making it move away from the channel region.
Further, the second doped region also has both of the accepter and the donor. A concentration of the acceptor in the second doped region is lower than a concentration of the acceptor in the first region when the semiconductor device is a N type transistor, in which a concentration of the donor in the first doped region is higher than a concentration of the acceptor in the first doped region. A concentration of the donor in the second region is lower than a concentration of the donor in the first region when the semiconductor device is a P type transistor, in which a concentration of the donor in the first doped region is lower than the concentration of the acceptor in the first doped region.
The semiconductor device of the invention can be top-gate structure or bottom-gate structure.
The method for fabricating the semiconductor device, comprising providing a substrate; forming a semiconductive layer having a crystallization promoting material on the substrate; forming a channel region, a first doped region, and a second doped region in the semiconductive layer, the second doped region positioned between the first doped region and the channel region, wherein the first doped region has two dopants including a donor and a acceptor, the second doped region has a dopant selected from one of the donor and the acceptor; forming a gate electrode insulated from the channel region; and recovering the semiconductor device with a heat treatment so as to allow the crystallization promoting material to be moved from the channel region.
The acceptor comprises at least one element selected from MA group elements including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth(Bi). The donor comprises at least one element selected from VA group elements including boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).
The methods for fabricating the semiconductor device of top-gate structure and bottom-gate structure will be respectively elucidated with drawings in following paragraph since there is a bit difference between them.
The topgate semiconductor device 100 of the first embodiment can be fabricated by many processes. Four processes are taken for example, but one skilled in the art of the time knows that the invention is not limited these examples.
First, a substrate 110 with a semiconductive layer 120 having a crystallization promoting material formed thereon is provided, and a gate insulating layer 130 is formed on the semiconductive layer 120, as shown in
Next, a conductive layer 142 is formed on the gate insulating layer 130, and an patterning a photoresist layer 144 is formed and patterned on the conductive layer 142, as shown in
These two implantations will be disclosed in detail to explain how to fabricate the semiconductor device 100 whose first doped region 124 has a donor and an acceptor and the second doped region 126 thereof has a dopant which is selected from one of the donor and the acceptor. For example, one of the dopants is implanted in the first doped region 124 during the first implantation, and the other of the dopants is implanted in the first doped region 124 and the second doped region 126 during the second implantation. Thus, the first doped region 124 has the donor and the acceptor, the second doped region 126 has a dopant selected from one of the donor and the acceptor. If the semiconductor device 100 is a P type transistor, the donor will be doped in the firs doped region 124 during the first implantation and the acceptor will be doped in both first and second doped region 124 and 126 during the second implantation. P type transistor therefore has a first doped region 124 with both donor and acceptor and second doped region 126 with acceptor only. In addition, both the donor and the acceptor are implanted during the first implantation, and only one of the donor and the acceptor is implanted during the second implantation. It also results in the same structure of the semiconductor device.
On the other hand, the second doped region 126 of the semiconductor device can also be doped with both of the accepter and the donor. For example, one of the donor and the acceptor is implanted during the first implantation, and both of the donor and the acceptor, in which the one has already implanted during the first implantation 124 has lower concentration than that applied during the first implantation, are implanted during the second implantation. If the semiconductor device 100 is a P type transistor, only donor will be doped in the firs doped region 124 during the first implantation, and acceptor and donor, whose dosage is lighter than that doped in the first implantation, will be doped in both first and second doped region 124 and 126 during the second implantation. In the P type transistor, both of the first and second doped regions 124 and 126 are doped with donor and acceptor, but concentration of donor in the second doped region 126 is lower than that in the first doped region 124. Moreover, the acceptor and donor can also be implanted during the first implantation since it will not change the concentration of donor in the first and second doped region. Therefore, the first doped region 124 and the second doped region 126 are formed during the first and second implantations, as shown in
Finally, recovering the semiconductor device 100 with a heat treatment, such as excimer laser annealing (ELA) and rapid thermal annealing (RTA), so as to allow the crystallization promoting material to be moved away from the channel region 122, as shown in
The method of fabricating the semiconductive device according to the second example is similar to that of the first example except the timing of two implantations. Steps same as those in the first example will not be repeated in the following paragraph.
The method of fabricating the semiconductive device according to the third example is similar to that of the first example except the timing of two implantations. Steps same as those in the first example will not be repeated in the following paragraph.
The method of fabricating the semiconductive device according to the forth example is similar to that of the third example except the timing of two implantations. Steps same as those in the third example will not be repeated in the following paragraph.
The methods for fabricating the semiconductor device of bottom-gate structure will be elucidated with drawings in following paragraph.
As described hereinbefore, the semiconductor device and the method for fabricating the same has many advantages. The first and second doped regions are capable of attracting the crystallization promoting material for make it move away from the channel region. Especially, the second doped region plays a role of buffer to receive most of diffused crystallization promoting material, so that little crystallization promoting material reach the channel region. The crystallization promoting material seldom exists in the channel region, and the semiconductor device therefore has improved character. Compared with the prior art, the method disclosed in the first example needs no additional mask so as to reduce the cost.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
