The invention relates to a method for fabricating semiconductor device, and more particularly to a method of using cleaning process to form void between spacer and substrate.
In order to increase the carrier mobility of semiconductor structure, it has been widely used to apply tensile stress or compressive stress to a gate channel. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region of PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of NMOS transistor.
Current approach of forming MOS transistor having epitaxial layer is usually achieved by removing part of the interlayer dielectric (ILD) layer to form contact hole after forming an epitaxial layer, and then depositing metals into the contact hole to form a contact plug. This order however easily damages the surface of the epitaxial layer and affects the performance of the device substantially. Hence, how to improve the current fabrication to resolve this issue has become an important task in this field.
According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps off forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses.
According to another aspect of the present invention, a semiconductor device includes: a gate structure on a substrate; two portions of an epitaxial layer adjacent to two sides of the gate structure; and a cap layer on the epitaxial layer, wherein the cap layer comprises a planar top surface and an inclined sidewall.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
In this embodiment, the substrate 12 could be a semiconductor substrate such as a silicon substrate, an epitaxial substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. The gate dielectric layer 18 could include silicon oxide (SiO2), silicon nitride (SiN), or high-k dielectric material; the gate material layer 20 could include metal, polysilicon, or silicide; the material of hard mask 22 could be selected from the group consisting of SiO2, SiN, SiC, and SiON.
According to an embodiment of the present invention, a plurality of doped wells or shallow trench isolations (STIs) could be selectively formed in the substrate 12. Despite the present invention pertains to a planar MOS transistor, it would also be desirable to apply the process of the present invention to non-planar transistors, such as FinFET devices, and in such instance, the substrate 12 shown in
Next, at least one spacer is formed on sidewalls of each of the gate structures 14 and 16, and an optional lightly doped ion implantation processes is conducted along with a rapid thermal annealing processes performed at about 930° C. to active the dopants implanted in the substrate 12. This forms lightly doped drains 24 in the substrate 12 adjacent to two sides of the spacers. In this embodiment, the spacer formed on sidewalls of each of the gate structures 14, 16 is preferably a composite spacer further including a spacer 26 disposed or directly contacting sidewalls of the gate structures 14, 16 or gate electrodes, a spacer 28 disposed on sidewalls of the spacer 26, and a spacer 30 disposed on sidewalls of the spacer 28, in which the innermost spacer 26 includes an I-shape cross-section, the middle spacer 28 includes a L-shape cross-section, and the outermost spacer 30 includes a lower portion 72 with an I-shape cross-section and an upper portion 74 with a half-arc shape. In this embodiment, the innermost spacer 26 and the middle spacer 28 could be made of same material or different materials, the innermost spacer 26 and the outermost spacer 30 could be made of same material or different material, and all three spacers 26, 28, 30 could include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or combination thereof. The middle spacer 28 and the outermost spacer 30 on the other hand are preferably made of different materials, in which the middle spacer 28 in this embodiment is preferably made of silicon oxide while the outermost spacer 30 is made of silicon nitride.
Next, as shown in
Next, as shown in
It should also be noted that the cleaning process 34 conducted at this stage not only trims the outermost spacer 30 but also removes part of the substrate 12 surface directly contacting the L-shape spacer 28. Preferably, the planar surface of the substrate 12 which was parallel to the bottom surface of the gate structures 14, 16 is partially removed during the cleaning process 34 to form at least an inclined surface 38, in which an angle included by the inclined surface 38 and the top surface of the substrate 12 (or more specifically the surface contacted by the bottom of the spacer 28 and the substrate 12) is greater than 90 degrees but less than 180 degrees. In this embodiment, the etchant used in the cleaning process 34 could include but not limited to for example diluted hydrofluoric acid (dHF) and/or TMAH.
Next, as shown in
In this embodiment, the epitaxial layer 40 could also be formed to include different material depending on the type of transistor being fabricated. For instance, if the MOS transistor being fabricated were to be a PMOS transistor, the epitaxial layer 40 could be made of material including but not limited to for example SiGe, SiGeB, or SiGeSn. If the MOS transistor being fabricated were to be a NMOS transistor, the epitaxial layer 40 could be made of material including but not limited to for example SiC, SiCP, or SiP. Moreover, the SEG process could also be adjusted to form a single-layered epitaxial structure or multi-layered epitaxial structure, in which heteroatom such as germanium atom or carbon atom of the structure could be formed to have gradient while the surface of the epitaxial layer 40 is preferred to have less or no germanium atom at all to facilitate the formation of silicide afterwards.
Next, an ion implantation process is conducted to form source/drain regions 44 in part or the entire epitaxial layer 40. According to an embodiment of the present invention, the source/drain regions 44 could also be formed insituly during the SEG process. For instance, the source/drain regions 44 could be formed by implanting p-type dopants during formation of a SiGe epitaxial layer, a SiGeB epitaxial layer, or a SiGeSn epitaxial layer for PMOS transistor, or could be formed by implanting n-type dopants during formation of a SiC epitaxial layer, SiCP epitaxial layer, or SiP epitaxial layer for NMOS transistor. By doing so, it would be desirable to eliminate the need for conducting an extra ion implantation process for forming the source/drain region. Moreover, the dopants within the source/drain regions 44 could also be formed with a gradient, which is also within the scope of the present invention.
Next, as shown in
Next, as shown in
Next, a replacement metal gate (RMG) process is conducted to transform the gate structures 14, 16 into metal gates. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process, such as using etchants including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard masks 22, gate material layer 20 and even gate dielectric layer 18 from gate structures 14, 16 for forming recesses (not shown) in the ILD layer 54. Next, a selective interfacial layer 56 or gate dielectric layer, a high-k dielectric layer 58, a work function metal layer 60, and a low resistance metal layer 62 are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer 62, part of work function metal layer 60, and part of high-k dielectric layer 58 to form gate structures 14, 16 made from metal gates 64, 66. In this embodiment, each of the gate structures 14, 16 or metal gates fabricated through high-k last process of a gate last process preferably includes an interfacial layer 56 or gate dielectric layer (not shown), a U-shaped high-k dielectric layer 58, a U-shaped work function metal layer 60, and a low resistance metal layer 62.
In this embodiment, the high-k dielectric layer 58 is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer 58 may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof.
In this embodiment, the work function metal layer 60 is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer 60 having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer 60 having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer 60 and the low resistance metal layer 62, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer 62 may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.
Next, part of the high-k dielectric layer 58, part of the work function metal layer 60, and part of the low resistance metal layer 62 are removed to form recesses (not shown), an hard masks 68 are then formed into the recesses so that the top surfaces of the hard masks 68 and ILD layer 54 are coplanar. The hard masks 68 could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof.
Next, a contact plug formation could be conducted to form contact plugs 70 electrically connected to the source/drain regions 44. In this embodiment, the formation of contact plugs 70 could be accomplished by removing part of the ILD layer 54 and part of the CESL to form contact holes (not shown), and then depositing a barrier layer (not shown) and a metal layer (not shown) into the contact holes. A planarizing process, such as CMP is then conducted to remove part of the metal layer, part of the barrier layer, and even part of the ILD layer 54 to form contact plugs 70, in which the top surface of the contact plugs 70 is even with the top surface of the ILD layer 54. In this embodiment, the barrier layer is selected from the group consisting of Ti, Ta, TiN, TaN, and WN, and the metal layer is selected from the group consisting of Al, Ti, Ta, W, Nb, Mo, and Cu.
Referring again to
Viewing from a more detailed perspective, the spacer 26 shown in
Preferably, the three spacers 26, 28, 30 are made of different materials, in which the middle spacer 28 is preferably made of silicon oxide, the outermost spacer 30 is made of silicon nitride, and the innermost spacer 26 could be made from SiO2, SiN, SiON, or SiCN depending on the demand of the product.
Moreover, the top or more specifically topmost surface of the epitaxial layer 40 is preferably higher than the top surface of the substrate 12 and sidewalls of the epitaxial layer 40 preferably include protruding portions 42 on the inclined surface 38 of the substrate 12, in which the protruding portions 42 and sidewalls of the epitaxial layer 40 together constitute jagged pattern as the protruding portions 42 extend toward the gate structures 14, 16 and away from the epitaxial layer 40. The cap layer 46 disposed on top of the epitaxial layer 40 preferably includes a planar top surface 48 parallel to the top surface of the substrate 12 or bottom surface of the gate structures 14, 16, two inclined sidewalls 50 connected to the planar top surface 48, and two vertical sidewalls 52 directly contacting the spacers 28 and connected to the two inclined sidewalls 50. Since the cap layer 46 is extended into lower portions of the spacer 30, part of the cap layer 46 preferably contacts the spacers 28, 30 directly. In contrast to the two vertical sidewalls 52 not aligning the sidewalls of the spacers 28, 30 as shown in
Referring to
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Number | Date | Country | Kind |
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108103436 | Jan 2019 | TW | national |
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Number | Date | Country | |
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20200243664 A1 | Jul 2020 | US |