Patent Application
20100283104
The present invention relates to semiconductor devices for use in, e.g., liquid crystal displays (LCDs), and manufacturing methods thereof.
In recent years, so-called active matrix drive devices for driving liquid crystal display (LCD) panels, organic electroluminescence (EL) panels, and the like are known in the art. Such active matrix drive devices are semiconductor devices in which thin film transistors (TFTs) containing amorphous silicon (amorphous Si or a-Si) or polysilicon (p-Si) are formed on arbitrary substrates larger than silicon (Si) wafers, such as glass substrates and quartz substrates. Formation of higher performance Si devices has been studied in order to integrate peripheral drivers, or systems for which higher performance is required, such as memories, microprocessors, image processors, and timing controllers, on substrates.
In particular, polysilicon has received attention as a material that is used to integrate peripheral drivers having high mobility and operating at a high speed. However, polysilicon has localized levels in bandgaps due to crystalline imperfection, and has defects and localized levels near grain boundaries, causing problems such as reduced mobility, an increased S coefficient (subthreshold coefficient), and the like.
Moreover, in the case of forming TFTs on those substrates, such as glass substrates, whose processing accuracy is lower than that of Si wafers, miniaturization of devices is limited due to the relatively low processing accuracy. This makes it difficult to integrate systems requiring more sophisticated element portions, such as memories, microprocessors, image processors, and timing controllers, on the glass substrates.
As a solution to the above problems, Patent Document 1, for example, discloses a technique for transferring an element portion, which includes a monocrystalline Si TFT formed on a silicon substrate, onto a glass substrate or the like. The technique of Patent Document 1 will be described with reference to
First, a monocrystalline Si TFT 130 of an element portion 120 is formed on a silicon substrate 101. More specifically, as shown in
Next, by using the gate electrode 104 as a mask, an impurity element is ion implanted into the silicon substrate 101 to form lightly doped impurity regions 105. Then, sidewalls 106 are formed, and an impurity element is ion implanted into the silicon substrate 101 to form heavily doped impurity regions 107.
Thereafter, as shown in
Subsequently, as shown in
PATENT DOCUMENT 1: Japanese Published Patent Application No. 2004-165600
However, in the manufacturing method of Patent Document 1, the types of layers laminated in a region covered by the gate electrode 104 are different from those laminated in a region not covered by the gate electrode 104 on the silicon substrate 101. Thus, when hydrogen is ion implanted into the silicon substrate 101, the ion implantation depth can vary between these regions, whereby the delamination layer can be formed at different depths in these regions. This makes it difficult to control the final thickness of the silicon layer after the transfer process.
This problem is particularly significant in the case where gate electrodes are formed by silicide (especially polycide formed by silicidating polysilicon gate electrodes) which is commonly used in transistors in recent years.
Moreover, in the manufacturing method of Patent Document 1, hydrogen ions are implanted after formation of the planarizing film that covers the gate electrode. Thus, the hydrogen ions need to be accelerated at high energy, whereby the hydrogen ions are implanted in an excessively large area. In addition, since a hydrogen ion implantation region is formed so as to reflect the thickness distribution of the planarizing film, it is difficult to maintain a uniform implantation depth of the hydrogen ions.
The present invention was developed in view of the above problems, and it is a primary object of the present invention to reduce a variation in implantation depth of a delamination material in a base layer to form as flat a delamination layer as possible.
In order to achieve the above object, according to the present invention, a delamination layer is formed before patterning of an electrode.
More specifically, a method for manufacturing a semiconductor device according to the present invention includes: an element portion forming step of forming in a base layer an element portion that includes at least a part of an element including an electrode; a delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer; a bonding step of bonding to the substrate the base layer having the element portion formed therein; and a separating step of separating and removing along the delamination layer a part of the base layer bonded to the substrate, where the element portion is not formed, wherein the element portion forming step includes an insulating film forming step of forming an insulating film on a surface of the base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form the electrode, and the delamination layer forming step is performed before the electrode forming step.
The method may further include a metal film forming step of laminating a metal film on a surface of the conductive layer, and in the electrode forming step, the conductive layer and the metal film may be patterned to form the electrode.
It is preferable that the surface of the conductive layer be planarized in the conductive layer forming step.
It is preferable that the delamination layer forming step be performed after the conductive layer forming step.
The conductive layer may be made of polysilicon.
It is preferable that the delamination material be hydrogen or an inert element.
It is preferable that the base layer be a monocrystalline silicon layer.
The substrate may be a glass substrate.
The electrode may form at least a part of a gate electrode of a MOS transistor.
It is preferable that a surface of the base layer, which is to be bonded to the substrate, be planarized in advance in the bonding step.
A semiconductor device according to the present invention includes: a substrate; a base layer bonded to the substrate with a part of the base layer being separated and removed along a delamination layer containing a delamination material; and an element portion including at least a part of an element, and formed in the base layer, wherein the delamination layer is formed in the base layer before an electrode of the element is patterned.
The electrode may be formed by a silicon layer portion and a metal layer portion laminated thereon.
It is preferable that the delamination material be hydrogen or an inert element.
It is preferable that the base layer be a monocrystalline silicon layer.
The substrate may be a glass substrate.
[Functions]
Functions of the present invention will be described below.
When manufacturing the above semiconductor device, an element portion, which includes at least a part of an element including an electrode, is formed in a base layer such as, e.g., a monocrystalline silicon layer, in an element portion forming step.
An insulating film forming step, a conductive layer forming step, and an electrode forming step are performed in the element portion forming step. In the insulating film forming step, an insulating film is formed on the surface of the base layer. Then, in the conductive layer forming step, a conductive layer is uniformly formed on the surface of the insulating film. The conductive layer may be made of, e.g., polysilicon. The surface of the conductive layer may be planarized in this conductive layer forming step. This enables a flat delamination layer to be formed in a later delamination layer forming step.
Then, in the electrode forming step, the conductive layer is patterned to form an electrode. The electrode may be formed by, e.g., a silicon layer portion and a metal layer portion laminated thereon. In the case where the electrode has the metal layer portion, the electrode is formed by first performing a metal film forming step of laminating a metal film on the surface of the conductive layer, and then patterning the conductive layer and the metal layer in the electrode forming step. This electrode later forms at least a part of a gate electrode in a MOS transistor.
The delamination layer forming step is performed before the electrode forming step. In the delamination layer forming step, a delamination material such as, e.g., hydrogen or an inert element is ion implanted into the base layer to form a delamination layer in the base layer. This delamination layer forming step is preferably performed after, e.g., the conductive layer forming step. This can make the delamination layer to be less affected by heat that is applied to the base layer in other processes.
Then, a bonding step is performed to bond the base layer, having the element portion formed therein, to a substrate such as, e.g., a glass substrate. In this bonding step, the surface of the base layer, which is to be bonded to the substrate, may be planarized in advance. This enables the base layer and the substrate to be bonded together by self-bonding due to the van der Waals force.
Subsequently, a separating step is performed to separate and remove along the delamination layer a part of the base layer bonded to the substrate, where the element portion is not formed. The semiconductor device is formed in this manner.
According to the present invention, the delamination layer is formed before the electrode is patterned. This reduces a variation in implantation depth of the delamination material in the base layer due to the shape of the electrode, thereby enabling a flat delamination layer to be formed in the base layer.
Moreover, since it is not necessary to implant a delamination material via a planarizing film that covers the electrode, the delamination layer can be formed at a shallow position at relatively low energy. As a result, the delamination layer can be formed at a uniform depth while suppressing damage to the base layer.
In addition, especially in the case where the electrode is formed by a conductive layer of, e.g., polysilicon and a metal film, the flatness of the delamination layer can be improved while increasing the conductive property of the electrode.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the following embodiments.
The semiconductor device S is formed directly on a glass substrate 38 of, e.g., a display panel of an LCD, not shown, and is used as various functional circuits, such as, e.g., a driver circuit for driving and controlling a plurality of pixels of the display panel.
Although not shown in the figure, the LCD includes: a TFT substrate having a plurality of TFTs (transistors) formed thereon; a counter substrate provided so as to face the TFT substrate; and a liquid crystal layer interposed between the TFT substrate and the counter substrate. A common electrode, which is made of, e.g., indium tin oxide (ITO) or the like, color filters, and the like are formed on a glass substrate of the counter substrate. On the other hand, the plurality of TFTs, pixel electrodes, and the like are formed on the glass substrate 38 of the TFT substrate.
As shown in
Note that, in the case where the semiconductor device S is used in transmissive LCDs, transparent substrates such as the glass substrate 38 are preferable as the substrate 38. However, in the case where the semiconductor device S is used in other LCDs, other substrates such as a monocrystalline silicon semiconductor substrate can be used as the substrate 38.
As shown in
Note that although only one PMOS transistor 56 is shown in
The base layer 1 has an active region 51. The active region 51 has a lightly doped drain (LLD) structure formed by P-type lightly doped impurity regions 23 and P-type heavily doped impurity regions 30. The P-type lightly doped impurity regions 23 are formed on both sides (the left and right sides in the figure) of a channel region 13. The P-type heavily doped impurity regions 30 are formed outside the lightly doped impurity regions 23.
The base layer 1 is a semiconductor layer made of, e.g., a monocrystalline silicon semiconductor. Note that the base layer 1 can be configured so as to include at least one selected from the group consisting of Group IV semiconductors, Group II-VI compound semiconductors, Group III-V compound semiconductors, Group IV-IV compound semiconductors, alloys containing homologous elements thereof, and oxide semiconductors, instead of the monocrystalline silicon semiconductor layer.
As described below, a part of the base layer 1 is separated and removed along a delamination layer, which is formed by ion implantation of a delamination material such as hydrogen. The base layer 1 is thinned by separating and removing the part of the base layer 1 in this manner by a heat treatment. As described below, the delamination layer is formed in the base layer 1 before a gate electrode 17 is patterned.
As shown in
The gate electrode 17, which is made of, e.g., polysilicon or the like, and sidewalls 24 are formed between the planarizing film 31 and the gate oxide film 16. The gate electrode 17 faces the channel region 13 with the gate oxide film 17 interposed therebetween. On the other hand, the sidewalls 24 are positioned on both sides of the gate electrode 17, and face the lightly doped impurity regions 23 with the gate oxide film 16 interposed therebetween.
Contact holes 35 are formed so as to extend through the planarizing film 31 at positions vertically overlapping the heavily doped impurity regions 30. A source electrode 36 and a drain electrode 36 are formed in the contact holes 35. The source electrode 36 and the drain electrode 36 are metal electrodes.
[Manufacturing Method]
A manufacturing method of the semiconductor device S will be described below.
First, in an element portion forming step, an element portion D, which includes at least a part of a PMOS transistor 56 as an element, is formed in a base layer 1, which is, e.g., a monocrystalline silicon semiconductor layer. That is, the element portion D is formed in a wafer of a silicon substrate 1 (which corresponds to the base layer 1) made of a monocrystalline silicon semiconductor. As described later, the element portion forming step includes an insulating film forming step, a conductive layer forming step, and an electrode forming step.
For example, a heat treatment is performed at about 900 to 1,000° C. in an oxidizing atmosphere to form a thermal oxide film on the surface of the silicon substrate 1. Thereafter, a silicon nitride film is formed on the surface of the thermal oxide film by a chemical vapor deposition (CVD) method or the like, and then the silicon nitride film and the thermal oxide film are patterned. The PMOS transistor 56 is later formed in a region where the silicon nitride film and the thermal oxide film are left.
Then, as shown in
Then, as shown in
Thereafter, a delamination layer forming step is performed before the electrode forming step described below. As shown in
As shown in
Then, the electrode forming step is performed. In this step, as shown in
Thereafter, as shown in
Then, a SiO2 film is formed by a CVD method or the like so as to cover the gate oxide film 16, the LOCOS oxide films 10, and the like. The SiO2 film is subjected to anisotropic dry etching to form sidewalls 24 of SiO2 on both sides (the left and right sides in the figure) of the gate electrode 17, as shown in
Then, as shown in
Thereafter, as shown in
Subsequently, as shown in
Then, a protective insulating film 37 is formed over the surface of the planarizing film 36 so as to cover the PMOS transistor 56. The element portion forming step of forming the element portion D in the base layer 1 as the silicon substrate 1 is performed in this manner.
Thereafter, a bonding step is performed. In the bonding step, the silicon substrate 1 (the base layer 1), having the element portion D formed therein, is bonded to a substrate 38.
For example, a glass substrate 38 is used as the substrate 38. More specifically, the surface of the silicon substrate 1, which is to be bonded to the glass substrate 38, is polished and planarized in advance by a CMP method or the like. Then, the respective surfaces of the protective insulating film 37 and the glass substrate 38 are cleaned by Standard Clean-1 (SC-1). Then, the element portion D is aligned with the glass substrate 38, and the silicon substrate 1 (the base layer 1) and the glass substrate 38 are bonded together at the surface of the protective insulating film 37 by self-bonding due to the van der Waals force.
Then, a separating step is performed. In the separating step, as shown in
Then, the delamination layer 33 is removed by etching or the like, and the base layer 1 is thinned by etching, CMP, or the like until the LOCOS oxide films 10 are exposed, whereby element isolation is performed. Then, a heat treatment is performed to activate the impurity elements. The semiconductor device S is manufactured in this manner.
As described above, according to the first embodiment, the delamination layer 33 is formed before the gate electrode 17 is patterned. This reduces a variation in implantation depth of hydrogen 32 into the silicon substrate 1 (the base layer 1) due to the shape of the gate electrode 17, in the region where the PMOS transistor 56 is to be formed. As a result, a flat delamination layer 33 can be formed in the silicon substrate 1 in this region.
Incidentally, ion implantation of hydrogen 32 is conventionally performed after formation of a planarizing film that covers the gate electrode 17. Thus, hydrogen needs to be implanted to a relatively deep position from the surface of the planarizing film in order to form the delamination layer. This not only causes hydrogen ions to be implanted in an excessively large area, but also forms a hydrogen ion implantation region reflecting the thickness distribution of the planarizing film. Thus, it is difficult to maintain a uniform implantation depth of hydrogen ions.
On the other hand, according to the first embodiment, hydrogen is ion implanted before the gate electrode 17 is patterned. This eliminates the need to form such a planarizing film. Thus, hydrogen can be ion implanted at relatively low energy to a relatively shallow position from the surface of the polysilicon layer 14 without being spread excessively, whereby the delamination layer can be formed appropriately. As a result, in the region where the PMOS transistor 56 is to be formed, a flat delamination layer 33 can be formed at a uniform depth while suppressing damage to the silicon substrate 1.
Moreover, since the delamination layer forming step is performed after the conductive layer forming step, the delamination layer 33 can be made to be less affected by heat applied to the silicon substrate 1 (the base layer 1) in other processes. As a result, the function of the delamination layer 33 can be maintained sufficiently until the separating step.
The second embodiment is different from the first embodiment in that the polysilicon layer 14 has a convex surface in the first embodiment, whereas the surface of the polysilicon layer 14 is planarized in the second embodiment.
More specifically, when manufacturing the semiconductor device S of the second embodiment, the element portion forming step is performed similarly to the first embodiment until the insulating film forming step. Then, in the conductive layer forming step, as shown in
Then, as in the first embodiment, the delamination layer forming step is performed before the electrode forming step. More specifically, as shown in
Thereafter, the electrode forming step is performed as in the first embodiment. In this step, as shown in
Subsequently, as in the first embodiment, as shown in
Then, as shown in
As described above, in the second embodiment as well, the delamination layer 33 is formed before the gate electrode 17 is patterned. Thus, advantages similar to those of the first embodiment can be obtained. Moreover, in the second embodiment, the surface of the polysilicon layer 14 is planarized in the conductive layer forming step. Thus, the entirely flat delamination layer 33 can be formed in the later delamination layer forming step.
The third embodiment is different from the first embodiment in that the gate electrode 17 is made only of polysilicon in the first embodiment, whereas the gate electrode 17 is formed by a polysilicon layer and a metal layer in the third embodiment.
More specifically, as shown in
When manufacturing the semiconductor device S of the third embodiment, in the element portion forming step, the conductive layer forming step is performed after the insulating film forming step to uniformly form a polysilicon film 14 as a conductive layer on the surface of the gate oxide film 16, as shown in
Thereafter, as shown in
Subsequently, as in the first embodiment, as shown in
As described above, according to the third embodiment as well, the delamination layer 33 is formed before the gate electrode 17 is patterned. Thus, advantages similar to those of the first embodiment can be obtained. Moreover, in the third embodiment, the gate electrode 17 is formed by the silicon layer portion 19 and the metal layer portion 20 and is silicidated, whereby the resistance value of the gate electrode 17 can be reduced. That is, the flatness of the delamination layer 33 can be improved while increasing the conductive property of the gate electrode 17. Moreover, performing the heat treatment for silicidation before hydrogen ion implantation can prevent a reduction in function of the delamination layer 33 due to the heat treatment.
The fourth embodiment is different from the third embodiment in that the polysilicon layer 14 and the metal layer 18 have a convex surface in the third embodiment, whereas the respective surfaces of the polysilicon layer 14 and the metal layer 18 are planarized in the fourth embodiment.
More specifically, when manufacturing the semiconductor device S of the fourth embodiment, the element portion forming step is performed similarly to the first to third embodiments until the insulating film forming step. Then, in the conductive layer forming step, as shown in
Subsequently, the delamination layer forming step is performed as in the third embodiment. More specifically, as shown in
Then, as in the third embodiment, the electrode forming step is performed. In this step, as shown in
Subsequently, as in the third embodiment, as shown in
Thereafter, as shown in
As described above, according to the fourth embodiment as well, the delamination layer 33 is formed before the gate electrode 17 is patterned. Thus, advantages similar to those of the first embodiment can be obtained. Moreover, since the gate electrode 17 is formed by the silicon layer portion 19 and the metal layer portion 20, advantages similar to those of the third embodiment can also be obtained. In addition, in the fourth embodiment, the surface of the polysilicon layer 14 is planarized in the conductive layer forming step, so that the metal film 18 that is laminated on the polysilicon layer 14 also has a flat surface. Thus, the entirely flat delamination layer 33 can be formed in the later delamination layer forming step.
In the above embodiments, convex LOCOS oxide films 10 are formed by forming the LOCOS oxide films 10 on the flat silicon substrate 1. However, as shown in
In order to form the planarized LOCOS oxide films 10, as shown in
Thereafter, as shown in
Subsequently, as shown in
Then, as shown in
Planarizing the LOCOS oxide films 10 in this manner can improve the flatness of the entire delamination layer 33 that is formed in a later step.
Instead of the LOCOS oxide films 10, element isolation insulating layers may be formed by so-called shallow trench isolation (STI). For example, as shown in
Although MOS transistors are described as an example of the elements in the first embodiment, the present invention is not limited to this. That is, the present invention is similarly applicable to other elements having a locally protruding part.
The electrode that is formed in the electrode forming step does not necessarily form the entire gate electrode 17, but may form at least a part of a gate electrode in a MOS transistor.
In the above embodiments, the impurity elements ion-implanted into the silicon substrate 1 are thermally activated after the element portion D is bonded to the glass substrate 38. However, the present invention is not limited to this, and the impurity elements may be activated by a rapid heat treatment such as rapid thermal annealing (RTA) right after the impurity element is ion implanted into the heavily doped impurity regions.
As described above, the present invention is useful for semiconductor devices for use in, e.g., LCDs, and manufacturing methods thereof. The present invention is especially suitable in the case of forming a flat delamination layer in a base layer.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-341077 | Dec 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/003463 | 11/25/2008 | WO | 00 | 6/4/2010 |
