Semiconductor device and method for manufacturing the same

Abstract

An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows top and sectional views schematically illustrating a semiconductor device of a first embodiment.

FIG. 1B shows top and sectional views schematically illustrating a variant of the semiconductor device of the first embodiment.

FIG. 2 is a plan view illustrating a Si wafer on which the semiconductor device of the first embodiment is formed.

FIG. 3A is a structural diagram illustrating stress simulation on the semiconductor device of the first embodiment, together with a schematic top view thereof.

FIG. 3B is a structural diagram illustrating stress simulation on a conventional semiconductor device, together with a schematic top view thereof.

FIG. 4A is a diagram illustrating the results of the stress simulation on the semiconductor device of the first embodiment.

FIG. 4B is a diagram illustrating the results of the stress simulation on the conventional semiconductor device.

FIG. 5A is a diagram illustrating another results of the stress simulation on the semiconductor device of the first embodiment.

FIG. 5B is a diagram illustrating another results of the stress simulation on the conventional semiconductor device.

FIG. 6A is a sectional view illustrating some of the steps of manufacturing the semiconductor device of the first embodiment.

FIG. 6B is a sectional view illustrating another some of the steps of manufacturing the semiconductor device of the first embodiment.

FIG. 6C is a sectional view illustrating another some of the steps of manufacturing the semiconductor device of the first embodiment.

FIG. 7A shows top and sectional views schematically illustrating a semiconductor device of a second embodiment.

FIG. 7B shows top and sectional views schematically illustrating a variant of the semiconductor device of the second embodiment.

FIG. 8A shows top and sectional views illustrating some of the steps of manufacturing the semiconductor device of the second embodiment.

FIG. 8B shows top and sectional views illustrating another some of the steps of manufacturing the semiconductor device of the second embodiment.

FIG. 8C shows top and sectional views illustrating another some of the steps of manufacturing the semiconductor device of the present embodiment.

FIG. 9A shows top and sectional views schematically illustrating a semiconductor device of a third embodiment.

FIG. 9B shows top and sectional views schematically illustrating a variant of the semiconductor device of the third embodiment.

FIG. 10A is a sectional view illustrating some of the steps of manufacturing the semiconductor device of the third embodiment.

FIG. 10B is a sectional view illustrating another some of the steps of manufacturing the semiconductor device of the third embodiment,

FIG. 10C is a sectional view illustrating another some of the steps of manufacturing the semiconductor device of the third embodiment.

FIG. 11A is a graph illustrating stress-dependence of carrier mobility in an n-type MIS transistor having the channel length direction parallel to the <110> crystallographic axis direction and an n-type MIS transistor having the channel length direction parallel to the <100> crystallographic axis direction on a (100) Si wafer.

FIG. 11B is a graph illustrating another stress-dependence of carrier mobility in the n-type MIS transistor having the channel length direction parallel to the <110> crystallographic axis direction and the n-type MIS transistor having the channel length direction parallel to the <100> crystallographic axis direction on the (100) Si wafer.

FIG. 11C is a graph illustrating still another stress-dependence of carrier mobility in the n-type MIS transistor having the channel length direction parallel to the <110> crystallographic axis direction and the n-type MIS transistor having the channel length direction parallel to the <100> crystallographic axis direction on the (100) Si wafer.

Claims

1. A semiconductor device comprising: a MIS transistor including an active region formed in part of a surface of a semiconductor substrate, a gate electrode formed on the active region and source and drain regions formed in the active region;an insulating film covering at least the source region, the drain region and the gate electrode; anda pair of stress control regions formed on parts of the semiconductor substrate sandwiching the gate electrode in the gate width direction of the gate electrode, whereinthe direction of the length of a channel connecting the source region and the drain region is parallel to the <100> crystallographic axis of the semiconductor substrate andthe insulating film is not formed in the stress control regions or an insulating film thinner than the insulating film covering the source region, the drain region and the gate electrode is formed in the stress control regions.

2. A semiconductor device including a MIS transistor comprising: an active region formed in part of a surface of a semiconductor substrate;an isolation region formed in the surface of the semiconductor substrate to surround the active region;a gate electrode arranged in such a manner that its center in the gate width direction is located above the active region and its ends in the gate width direction overlap the isolation region;a source region and a drain region which are formed in the active region;an insulating film covering at least part of the gate electrode, the source region and the drain region; anda pair of stress control regions formed on the ends of the gate electrode in the gate width direction, whereinthe MIS transistor includes the active region, the gate electrode, the source region and the drain region,the direction of the length of a channel connecting the source region and the drain region is parallel to the <100> crystallographic axis of the semiconductor substrate andthe insulating film is not formed in the stress control regions or an insulating film thinner than the insulating film covering the part of the gate electrode, the source region and the drain region is formed in the stress control regions.

3. The semiconductor device of claim 2, wherein the pair of stress control regions formed on the ends of the gate electrode in the gate width direction further extend their sizes in the gate length direction of the gate electrode to overlap the surface of the semiconductor substrate.

4. The semiconductor device of claim 1, wherein a metal film or a second insulating film having different compressive stress from that of the insulating film is formed in the stress control regions.

5. The semiconductor device of claim 1, wherein the insulating film has internal tensile stress.

6. The semiconductor device of claim 1, wherein the stress control regions are longer than the gate electrode in the gate length direction of the gate electrode.

7. The semiconductor device of claim 1, wherein the MIS transistor is an n-channel type MIS transistor.

8. A method for manufacturing a semiconductor device comprising the steps of: (a) forming a gate electrode on an active region provided in a surface of a semiconductor substrate and forming a source region and a drain region in the active region to obtain a MIS transistor;(b) forming an insulating film on part of the surface of the semiconductor substrate where the active region is not formed, the gate electrode, the source region and the drain region;(c) providing a mask on a top surface of the insulating film such that a pair of parts of the top surface of the insulating film sandwiching the gate electrode in the gate width direction of the gate electrode are exposed;(d) performing etching after the step (c) to remove or reduce the thickness of the exposed parts of the insulating film; and(e) depositing an interlayer insulating film on the insulating film after the step (d).

9. A method for manufacturing a semiconductor device comprising the steps of: (f) forming a gate electrode on an active region provided in a surface of a semiconductor substrate and forming a source region and a drain region in the active region to obtain a MIS transistor;(g) forming an insulating film on part of the surface of the semiconductor substrate where the active region is not formed, the gate electrode, the source region and the drain region;(h) forming an interlayer insulating film on the insulating film;(i) forming a pair of holes in parts of a top surface of the interlayer insulating film sandwiching the gate electrode in the gate width direction of the gate electrode to penetrate the interlayer insulating film and the insulating film; and(j) filling the pair of holes with second insulating material having compressive stress different from that of the insulating film or metal.

10. The method of claim 9, wherein a pair of second holes are formed in part of the top surface of the interlayer insulating film sandwiching the gate electrode in the gate length direction to penetrate the interlayer insulating film and the insulating film simultaneously with the pair of first holes in the step (i) andthe pair of second holes are filled with metal in the step (j) to form electrodes for applying external voltage to the MIS transistor.