This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2011-66362, filed on Mar. 24, 2011, the entire contents of which are incorporated herein by reference.
Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same.
With further advancement in miniaturization in accordance with the demand to miniaturize a non-volatile semiconductor storage device, the aspect ratio of the height and the width of the gate structure are becoming higher in the gate pattern processing in the manufacturing of the non-volatile semiconductor storage device.
The reason for this is that the coupling ratio (Cr) needs to be raised in order to control a memory cell transistor due to increase in the mutual interference effect by reduction in the distance between the memory cell transistors of the non-volatile semiconductor storage device. In other words, in order to raise the coupling ratio, which is generally expressed as Cr=CIPD/(CIPD+CTNL), the capacity of the inter poly dielectric (IPD) covering a lower gate electrode (floating gate) is to be increased. To this end, the lower gate electrode is made higher to increase the contacting area of the lower gate electrode and the IPD, but this leads to increase in the aspect ratio at the time of the gate pattern processing since the height of the lower gate electrode increases. If the aspect ratio increases, the degree of difficulty in the processing of the gate pattern increases. The increased ratio also causes lowering of the yield due to gate pattern destruction, and the like in the manufacturing process such as cleaning.
In a select transistor of the non-volatile semiconductor storage device and a peripheral transistor positioned in a surrounding circuit region, the lower gate electrode and the upper gate electrode (control gate) are connected to obtain a desired structure while forming with the memory cell transistor. A groove called an EI (Etching Interpoly) is formed in the IPD for such connection. In this case, it is formed using a hard mask made of a thick oxide silicon film. The hard mask will be removed afterwards, but the upper gate electrode and the IPD are processed to form the EI groove while protecting the IPD with the upper gate electrode in advance, and furthermore, a polycrystalline silicon film is formed so as to fill the EI groove and cover the upper gate electrode, which is already formed, so that the IPD will not be eroded and degraded in the removal. Thus, the upper gate electrode needs to have a stacked structure of two layers, the upper gate electrode formed in advance and the polycrystalline silicon film formed thereon. Such a structure is one of the causes of the increase in the aspect ratio at the time of the gate pattern processing.
When forming a metal gate on the upper gate electrode, the metal gate is formed on the upper gate electrode having a stacked structure as described above, and hence the aspect ratio at the time of the gate pattern processing is further increased.
a) and 1(b) are a plan view of a semiconductor device according to an embodiment;
a) and 2(b) are a cross-sectional view of the semiconductor device according to the embodiment;
In one embodiment, a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device including a memory cell transistor in a first region of a substrate, and a select gate transistor in a second region of the substrate, the method including: forming a gate insulating film, a lower gate electrode, an inter-electrode insulating film, an upper gate electrode, and a hard mask on the substrate; forming a groove passing through the hard mask, the upper gate electrode and the inter-electrode insulating film, and reaching the lower gate electrode in the second region of the substrate; and forming a connection layer having a crystal structure which preferentially has a specific crystal orientation and that electrically connects between the lower gate electrode and the upper gate electrode, by being selectively crystal-grown while being subjected to an influence from a crystal structure of the lower gate electrode in the groove.
The embodiment will be hereinafter described with reference to the drawings. It should be recognized that the present invention is not limited to the embodiment. Common reference numerals are denoted on the portions commonly used throughout the drawings and their description will not be repeated. The drawings are schematic diagrams to facilitate the description and the understanding of the embodiment, and the shape, dimension, ratio, and the like may differ from the actual device in some places. The shape, dimension, ratio, and the like may be appropriately changed in a design, in consideration of the following description and the known arts.
A semiconductor device of the present embodiment will be described using
First, as shown in
The memory cell transistors and the select transistor are formed on the same well substrate. The upper gate electrodes of the memory cell transistors CG1 to CGn are connected to word lines WL1 to WLn continuously arrayed in a row direction. The upper gate electrode of the select transistor SG1 is connected to a selection line Q1 and the upper gate electrode of the select transistor SG2 is connected to a selection line Q2. One end of each word line WL has a connection pad for connecting with a peripheral circuit through a metal wiring and is formed on an element isolation film.
The NAND type flash memory 100 includes a plurality of bit lines BL and a plurality of word lines WL. The bit lines BL are extended in the direction of line B-B′ in
The NAND type flash memory 100 of the present embodiment will now be described with reference to
As shown in
Each memory cell transistor 41 includes a gate insulating film 3 made of, for example, a silicon oxynitride film formed on the silicon substrate 1, a lower gate electrode 4 made of, for example, a polycrystalline silicon film formed on the gate insulating film 3, and an upper gate electrode 10 made of, for example, a polycrystalline silicon film formed on the lower gate electrode 4 through an IPD (inter-electrode insulating film) 9. Furthermore, each memory cell transistor 41 includes a metal gate electrode 14 made from, for example, tungsten or tungsten silicide formed on the upper gate electrode 10. The lower gate electrode 4 is generally referred to as a floating gate, and the upper gate electrode 10 and the metal gate electrode 14 are generally referred to as a control gate.
Each select transistor 42 and each peripheral transistor (not shown) include the gate insulating film 3 made of, for example, a silicon oxynitride film formed on the silicon substrate 1, the lower gate electrode 4 made of, for example, a polycrystalline silicon film formed on the gate insulating film 3, and the upper gate electrode 10 made of, for example, a polycrystalline silicon film formed on the lower gate electrode 4 through the IPD 9. Each select transistor 42 and each peripheral transistor (not shown) also include the metal gate electrode 14 formed on the upper gate electrode 10.
To ensure the operations thereof, each select transistor 42 and each peripheral transistor (not shown) include a connection via (connection layer) 22 that passes through the IPD 9 to electrically connect the lower gate electrode 4 and the upper gate electrode 10 and that is selectively solid-phase grown made from, for example, silicon. The connection via 22 may be made from germanium or a mixture thereof other than silicon, or arsenic, phosphorous, boron, or the like may be doped to lower the contact resistance.
The selective solid-phase growth means crystal-growing while being influenced by the crystal structure of the crystal (lower gate electrode 4 made of polycrystalline silicon film) serving as a base, and forming a crystal structure preferentially having a specific crystalline orientation. Therefore, the connection via 22 has a crystal structure that preferentially has a specific crystalline orientation based on the crystal structure of the lower gate electrode 4. Thus, the interface and the crystal grain boundary are small in the connection via 22, and the interface and the crystal grain boundary are small between the connection via 22 and the lower gate electrode 4.
As apparent from
Furthermore, as apparent from
As apparent from
The method of manufacturing the NAND type flash memory 100 of the present embodiment will now be described with reference to
As shown in
As shown in
As shown in
As shown in
As shown in
After removing the oxide film 6, the buried insulating film 8 is formed to bury the trench 21 through the plasma CVD method to form an element separation structure generally referred to as STI (Shallow Trench Isolation). Furthermore, as shown in
As shown in
As shown in
The upper gate electrode 10 made of polycrystalline silicon film is then formed on the IPD 9, using LPCVD (Low Pressure Chemical Vapor Deposition) method.
In each select transistor 42 and each peripheral transistor, the upper gate electrode 10 and the lower gate electrode 4 need to be electrically connected. Therefore, in the present embodiment, the connection via 22 for electrically connecting the upper gate electrode 10 and the lower gate electrode 4 is formed, as will be described below.
As shown in
The photoresist 12 is patterned through the lithography method, and the hard mask 11, the upper gate electrode 10, and the IPD 9 are etched through the RIE method, thereby forming an EI groove 23 that passes through the upper gate electrode 10 and the IPD 9 and reaches the lower gate electrode 4. As shown in
Cleaning is then carried out. When cleaning by water is carried out after the dilute hydrofluoric treatment, a natural oxide film may form on the side surfaces and the bottom surface including the lower gate electrode 4 in the EI groove 23 and the side surfaces including the upper gate electrode 10, and hence alcohol cleaning using isopropanol is desirably carried out. After the cleaning, it is immediately carried into the device where the next step is carried out, and annealing is carried out in vacuum so that a silicon cleaned surface can be exposed on the side surfaces and the bottom surface by the lower gate electrode 4 in the EI groove 23 and the side surfaces by the upper gate electrode 10.
As shown in
The selective solid-phase growing is generally carried out through the CVD method. The film forming gas that is used is generally Si2H2Cl2, SiHCl3, or SiCl4, and such gases are used depending on a growing speed. The growing speed is suppressed when more the Cl is used, and hence the growing speed becomes slower in the order of Si2H2Cl2, SiHCl3, or SiCl4.
Furthermore, when doping in the connection via 22, for instance, when forming an n-type silicon connection via 22, PH3 or AsH3 is introduced, and when forming a p-type silicon connection via 22, B2H6 is introduced as the film forming gas.
Assume here that SiH2Cl2 and H2 that is capable of low temperature growth are used as the film growing gas, and the temperature is set between 700 and 900° C. and the pressure is set in a range from a few dozen to a few hundred Torr for the film forming condition. When such gases are used, reaction expressed with the following reaction formula occurs.
SiH2Cl2→SiCl2+H2
SiCl2+H2→Si+2HCl
As apparent from the above reaction formula, hydrogen chloride (HCl) is generated with the solid-phase growth of the silicon (Si). Silicon (Si) is deposited on the hard mask 11 to form an amorphous silicon film, but the amorphous silicon film on the hard mask 11 is more easily etched than the silicon crystal solid-phase grown in the EI groove 23, and is etched by the generated hydrogen chloride. Therefore, the silicon can be selectively solid-phase grown in the EI groove 23.
For instance, when the silicon having a thickness of 30 nm is to be selectively solid-phase grown in the EI groove 23 as the connection via 22, the film forming time is about one minute in the above condition (in a case where temperature is 750° C.), where the influence on the device element when the selective solid-phase growing is carried out is minor in such extent.
A method of depositing the silicon in the EI groove 23, and then causing migration with high temperature hydrogen annealing to form the connection via 22 can be used instead of carrying out the formation of the connection via 22 by introducing the chlorine based gas at the same time as the selective solid-phase growing. However, the method of introducing the chlorine based gas at the same time as the selective solid-phase growing as described above is preferable in view of the practical aspect and the temperature applied on the device.
As shown in
As shown in
The photoresist 17 is patterned using the lithography method, and furthermore, the patterned photoresist 17 is used as a mask to process the silicon nitride film 15 to a desired pattern. Thereafter, as shown in
A silicon dioxide film 18 is formed using a thermal oxidation method or a radical oxidation method to recover the damage formed in the IPD 9 by the etching through the RIE method. Generally, such oxidation step is called the post-oxidation step, and the silicon dioxide film 18 formed in this case is referred to as a post-oxide film. Subsequently, as shown in
According to the present embodiment, in each select transistor 42 and each peripheral transistor of the NAND type flash memory 100, the connection via 22 for electrically connecting the lower gate electrode 4 and the upper gate electrode 10 is formed by forming the EI groove 23 that passes through the IPD 9 and reaches the lower gate electrode 4 from the upper gate electrode, and selectively solid-phase growing the silicon in the EI groove 23, thereby the upper gate electrode 10 can be configured as a single layer. In other words, the upper gate electrode 10 can be avoided from becoming a stacked structure, whereby the aspect ratio at the time of the gate pattern processing can be reduced.
Furthermore, according to the present embodiment, the interface and the crystal grain boundary can be reduced in the connection via 22 as the connection via 22 is formed through the selective solid-phase growing. Furthermore, the interface and the crystal grain boundary can also be reduced between the connection via 22 and the lower gate electrode 4. Therefore, the resistance value of the connection via 22 can be lowered.
The IPD 9 can be avoided from being damaged as the IPD 9 is covered with the upper gate electrode 10 when forming the EI groove 23.
According to the present embodiment, the upper surface of the connection via 22 is in plane with the upper surface of the upper gate electrode 10 or is projected from the upper surface of the upper gate electrode 10. Hence, when using the silicide gate electrode consisting of silicide in place of the metal gate electrode 14, the reaction of the silicide material film and the upper gate electrode 10 in the manufacturing process, which will be described below, can be avoided from being suppressed.
In a first modification of the present embodiment, the NAND type flash memory 100 can be formed in the following manner when using the silicide gate electrode in place of the metal gate electrode 14. The first modification will be described with reference to
When removing the silicon nitride film, the silicon nitride film sometimes get into the recess shaped portion or the like at the upper surface of the connection via 22 and may remains therein when the upper surface of the connection via 22 is formed in the shape of a recess or when a seam is present at the upper surface of the connection via 22. The residual of the remaining silicon nitride film suppresses the reaction of the silicide material film and the upper gate electrode 10.
However, according to the first modification of the present embodiment, the upper surface of the connection via 22 is in plane with the upper surface of the upper gate electrode 10 or is projected out from the upper surface of the upper gate electrode 10. Thus, the residual of the silicon nitride film can be avoided from being generated, and hence the reaction of the silicon material film and the upper gate electrode 10 can be avoided from being suppressed.
In the first modification of the present embodiment, after the EI groove 23 is formed while protecting the IPD 9 with the upper gate electrode 10 in advance, the connection via 22 made from silicon is formed only in the EI groove 23, instead of forming the upper gate electrode having a two-layer stacked structure of the upper gate electrode formed in advance and the polycrystalline silicon film formed thereon by burying the polycrystalline silicon in the EI groove 23 and by covering the already formed upper gate electrode 10 with the polycrystalline silicon. Thus, degradation of reliability of the gate insulating film 3, as described below, can be avoided when using the silicide gate electrode.
When forming the polycrystalline silicon film so as to bury the EI groove 23 and cover the already formed upper gate electrode 10, a seam easily forms as it is formed on the groove at the portion on the EI groove 23 of the newly formed polycrystalline silicon film. When such a seam forms, the silicide material film gets into the seam when the silicide material film is formed on the newly formed polycrystalline silicon film. When the silicide material film that entered the seam contacts the lower gate electrode 4 made of polycrystalline silicon film and thermal processing is carried out in such state, the silicide material film that has got into the seam reacts with the lower gate electrode 4, thereby generating the silicide. When such silicide contacts the gate insulating film 3, properties such as the work function of the gate insulating film 3 change, and the reliability of the gate insulating film 3 degrades.
However, in the first modification of the present embodiment, the connection via 22 made from silicon is formed only in the EI groove 23 without using the above-described method, and thus the degradation of the reliability of the gate insulating film 3 can be avoided even if the silicide gate electrode is used.
In order to solve such problem, a method of forming a barrier metal in the EI groove 23 that passes through the upper gate electrode 10 and the IPD 9 and reaches the lower gate electrode 4 is considered, but the contact resistance between the upper gate electrode 10 and the lower gate electrode 4 increases if the barrier metal is formed. However, such problem does not arise according to the first modification of the present embodiment, and thus the barrier metal is not necessary and the contact resistance can be avoided from increasing.
In the present embodiment, after forming the EI groove, the silicon is selectively solid-phase grown in the EI groove 23 to form the connection via 22. In a second modification, on the other hand, a protective film covering the side walls of the EI groove 23 is formed, and then the connection via is selectively solid-phase grown. More specifically, in the second modification, a protective film that covers the side walls of the EI groove 23 including the lower gate electrode 4 and the upper gate electrode 10 is formed, and the connection via 22 is selectively solid-phase grown on the bottom surface of the EI groove 23 including the lower gate electrode 10. The connection via 22 is thus crystal-grown first so as to cover the upper part of the side walls of the EI groove 23 including the upper gate electrode 10 and blocks the EI groove 23, and a state in which a cavity forms at the lower part of the EI groove 23, that is, a state in which the connection via 22 is not connected with the lower gate electrode 4 can be avoided.
The present modification will be described with reference to
First, similar to the embodiment described above, the EI groove 23 shown in
As shown in
The protective film 16 covering the bottom surface of the EI groove 23 is then removed through the RIE method. Accordingly, the bottom surface of the EI groove 23 is exposed, and the side walls of the EI groove 23 including the lower gate electrode 4 and the upper gate electrode 10 is covered by the protective film 16, as shown in
Similar to the present embodiment, dilute hydrofluoric acid treatment and cleaning are carried out to remove the processing residual, and the silicon is selectively solid-phase grown in the EI groove 23. That is, the silicon is crystal-grown while being subjected to the influence of the crystal structure of the lower gate electrode 4 of the bottom surface of the EI groove 23 to form the connection via 22 having a crystal structure that preferentially has a specific crystal orientation based on the crystal structure of the lower gate electrode 4. The subsequent steps are similar to the previously described embodiment, and hence the description will not be repeated. The NAND type flash memory 100 having a cross-sectional view shown in
Therefore, according to the second modification, the protective film that covers the side walls of the EI groove 23 including the lower gate electrode 4 and the upper gate electrode 10 is formed, and the connection via 22 is selectively solid-phase grown on the bottom surface of the EI groove 23, so that the connection via 22 crystal grows first to cover the upper part of the side walls of the EI groove 23 including the upper gate electrode 10 thus blocking the EI groove 23. Accordingly, a state in which a cavity forms at the lower part of the EI groove 23, that is, a state in which the connection via 22 is not connected with the lower gate electrode 4 can be avoided.
In the second modification, the connection via 22 does not have a configuration of directly contacting the upper gate electrode 10, but the connection via 22 contacts the metal gate electrode 14 at the upper surface thereof since the metal gate electrode 14 is formed on the upper gate electrode 10 in the subsequent step. Therefore, the metal gate electrode 14 is electrically connected to the upper gate electrode 10, and the connection via 22 electrically connects the lower gate electrode 4 and the upper gate electrode 10 through the metal gate electrode 14.
The protective film 16 in the second modification may be formed in the following manner. The method of forming the protective film 16 will be described using
Similar to the embodiment described above, the EI groove 23 shown in
Then, as shown in
A part of the protective film 16 is then removed through the RIE method to expose the bottom surface of the EI groove 23. Therefore, as shown in
In the above-described embodiment, as well as first and second modifications, the silicon substrate does not necessarily be made from silicon and may be made of other materials. A semiconductor structure or the like may be formed on various substrates.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2011-066362 | Mar 2011 | JP | national |