Patent Application
20240120403
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0129049, filed on Oct. 7, 2022, and Korean Patent Application No. 10-2023-0131156, filed on Sep. 27, 2023, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated by reference herein in its entirety.
Example embodiments relate to a semiconductor device including a buffer and/or a method of manufacturing the semiconductor device.
Transistors are semiconductor devices that serve as electrical switches and are employed in various integrated circuit devices including memory devices, integrated circuit (IC) devices, logic devices, and/or the like. In order to increase the degree of integration of integrated circuit devices, the space occupied by transistors provided therein is rapidly reduced, and research has been conducted to reduce the size of transistors and maintaining or improving the performance of the integrated circuit devices.
One of the important parts in the transistor is a gate electrode. When a voltage such as a threshold voltage is applied to the gate electrode, a channel adjacent to the gate opens a current path, and when a voltage such as the threshold voltage is not applied to the gate electrode, the current path is closed to block a current flow. The performance of semiconductors depends on how much a leakage current is reduced and efficiently managed in gate electrodes and/or in channels. The larger the area in which the gate electrode and the channel that control the current in the transistor contact each other, the higher the power efficiency.
As the semiconductor process becomes smaller, the size of the transistor decreases, and the area where the gate electrode and the channel contact or overlap each other decreases, thereby causing problems due to a short channel effect. For example, phenomena such as one or more of threshold voltage variation, carrier velocity saturation, and deterioration of the subthreshold characteristics occur. Accordingly, a method of overcoming or reducing the impact of the short channel effect and/or effectively reducing the channel length is needed or desired.
Provided is a semiconductor device including a buffer.
Alternatively or additionally, provided is a method of manufacturing the semiconductor device including a buffer.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to some example embodiments, a semiconductor device includes a substrate, a lower electrode on the substrate, a metal oxide on or in the lower electrode, a first buffer on or in the metal oxide, an oxide channel on or in the first buffer, a gate insulating layer on, in, contacting, or adjacent to the oxide channel, a gate electrode on, in, contacting, or adjacent to the gate insulating layer, and an upper electrode on the gate electrode or the oxide channel. The first buffer is between the metal oxide and the oxide channel, the first buffer includes a silicide material, the upper electrode and the lower electrode are spaced apart from each other in a direction perpendicular to the substrate, and longitudinal direction of the oxide channel is arranged perpendicularly to the substrate.
The silicide material may include at least one of WSix (tungsten silicide), RuSix (ruthenium silicide), NiSix (nickel silicide), and/or TiSix (titanium silicide).
The first buffer may have a thickness of about 1 Angstrom or more and about 50 Angstroms or less.
The semiconductor device may further include a second buffer between the upper electrode and the oxide channel, the second buffer including a silicide material.
The semiconductor device may further include a second buffer between the upper electrode and the oxide channel and including at least one of molybdenum (Mo), gold (Au), platinum (Pt), rhodium (Rh), ruthenium (Ru), titanium (Ti), tantalum (Ta), and iridium (Ir).
The first buffer may directly contact both the metal oxide and the oxide channel.
The gate electrode may surround a perimeter of the oxide channel.
The oxide channel may include at least one of indium (In), zinc (Zn), tin (Sn), gallium (Ga), and hafnium (Hf).
The oxide channel may include In and Zn, and an atomic percent of In in a metal contact part of the oxide channel may be greater than or equal to the content of Zn in the metal contact part of the oxide channel.
The oxide channels may include a material selected from among InGaZnO, ZnO, ZrInZnO, InZnO, InGaZnO4, ZnSnO, ZnInO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgnO2, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5, TiSrO3, zinc indium oxide (ZIO), indium gallium oxide (IGO), and a combination thereof.
The lower electrode may include at least one of tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), antimony (Sb), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg).
The longitudinal direction of each of the oxide channel, the gate insulating layer, and the gate electrode may be arranged to be oriented in a direction perpendicular to the substrate, and each of the oxide channel, the gate insulating layer, and the gate electrode may be arranged in a horizontal direction with respect to the substrate.
The oxide channel may have a U-shaped cross-section.
The oxide channel may include a first oxide channel having an L shape in which the longitudinal direction of the oxide channel is arranged to be oriented in a direction perpendicular to the substrate, and a second oxide channel symmetrically arranged with respect to the first oxide channel in the perpendicular direction. The gate electrode may include a first gate electrode having a longitudinal direction arranged to be oriented in a direction perpendicular to the substrate and a second gate electrode that is symmetrically arranged with respect to the first gate electrode in the perpendicular direction.
The lower electrode, the metal oxide, the first buffer, and the oxide channel may have the same width.
According to various example embodiments, a method of manufacturing a semiconductor device includes providing a lower electrode on a substrate, depositing a first buffer on the lower electrode, depositing an oxide channel on the first buffer, depositing a gate insulating layer on or to contact the oxide channel, depositing a gate electrode on the gate insulating layer, and depositing an upper electrode on the oxide channel. The first buffer is between the lower electrode and the oxide channel, the buffer includes a silicide material, the upper electrode and the lower electrode are spaced apart from each other in a direction perpendicular to the substrate, and the longitudinal direction of the oxide channel may be arranged perpendicularly to the substrate.
The depositing of the first buffer on the lower electrode may include depositing a metal-silicon composite layer on the lower electrode, and forming the buffer by heat-treating the metal-silicon composite layer.
The silicide material may include at least one of WSix, RuSix, NiSix, and/or TiSix.
The depositing of an upper electrode on the oxide channel may include further depositing, on the oxide channel, a second buffer including a material with an oxidation reactivity less than that of the upper electrode, and depositing the upper electrode on the second buffer that includes the material with the oxidation reactivity less than that of the upper electrode.
The oxide channel may include In and Zn, and atomic percentage of In in a metal contact part of the oxide channel may be greater than or equal to atomic percentage of Zn in the metal contact part of the oxide channel.
The above and other aspects, features, and advantages of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, various embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, example embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Hereinafter, a semiconductor device including a buffer according to various example embodiments and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. The terms first, second, etc. may be used to describe various components, but the components should not be limited by terms. The terms are used only for the purpose of distinguishing one component from other components.
Singular expressions include plural expressions unless the context clearly means otherwise. In addition, when a part “contains” a component, this means that it may contain other components, rather than excluding other components, unless otherwise stated.
The use of the term “the” and similar indicative terms may correspond to both singular and plural.
Steps constituting the method may be performed in an appropriate order unless there is a clear statement that the steps should be performed in the order described. In addition, the use of all illustrative terms (e.g., etc.) is simply intended to detail technical ideas and, unless limited by the claims, the scope of rights is not limited due to the terms.
Recently, Si-based memory or logic devices have reached or may have reached the limit of high integration, and require or use a channel length of several tens or several nanometers, making it very important to reduce off-current. In addition, it may be possible to improve a subthreshold swing (SS) and/or an on/off current ratio and the like as the characteristics required to clearly distinguish an on/off state. Oxide semiconductor transistors used as large-area display driving devices may have very good characteristics (e.g., low off-current, low SS, and/or high on/off current ratio). Accordingly, a method of utilizing an oxide semiconductor device having such an advantage as a memory and/or logic device, and/or increasing the degree of integration has been recently proposed.
However, due to the short-channel effect caused by scaling down, it may be difficult to immediately apply the display driving device to the semiconductor-oriented device, and performance may vary. Typically, the size (e.g., a width such as a transistor width and/or length such as a transistor length) of the channel layer may be reduced to make it difficult to control the threshold voltage, and/or a contact area in which the channel meets the electrode may be reduced to increase a contact resistance.
In particular, when atomic layer deposition (ALD) technology is applied to deposit an oxide semiconductor on an electrode to a channel length of several tens of nanometers or less, the oxide semiconductor is deposited at a temperature higher than room temperature such as used in the ALD method. Therefore, contact resistance may increase due to a side reaction between a metal of the electrode and a reactant.
Table 1 below shows a comparison between the case of deposition by a sputtering method and the case of deposition by an ALD method.
Referring to Table 1 above, it may be seen that when an oxide channel is deposited by the ALD method, a saturation threshold voltage of Vth,sat and an Ion value are decreased and an SS value is increased, compared to when the oxide channel is deposited by a sputtering/physical vapor deposition method.
In various example embodiments, a (first) buffer may be inserted into a partial and/or the entire contact region where the oxide semiconductor and the electrode are in contact, and side reactions of electrodes occurring during the ALD process of the oxide semiconductor can be suppressed/improved, and device characteristics can be improved. The buffer may include a metal material or a silicide material having an oxidation reactivity less than that of the electrode material.
The buffer may include a metal-based material (e.g., TiN, molybdenum (Mo), gold (Au), platinum (Pt), rhodium (Rh), ruthenium (Ru), titanium (Ti), tantalum (Ta), and/or iridium (Ir)) that are less reactive with oxygen than the electrode material. The buffer may include a metal material having high reactivity with oxygen when the by-product formed during the oxidation reaction is a material having low resistance.
Alternatively or additionally, the buffer may include a silicide material (e.g., WSix (tungsten silicide), RuSix (ruthenium silicide), NiSix (nickel silicide), and/or TiSix (titanium silicide). A silicide material, and/or a conductive oxide such as indium tin oxide (ITO) may be included only at an interface part of the electrode.
The buffer may include a plurality of materials. For example, the buffer may include a multilayer structure of a silicide material and a metal-based material having lower reactivity with oxygen than an electrode material.
In a 3D structured semiconductor device (e.g., a vertical channel transistor (VCT) using an oxide semiconductor material as a channel, contact resistance may be lowered, and an oxide semiconductor material with a desired composition may be manufactured, by introducing a buffer capable of suppressing byproduct generation in a contact area where an oxide semiconductor and an electrode are in contact.
Referring to
The substrate 110 may be or may have a flat plate shape provided on a plane. A vertical direction (a Z direction) may be a direction perpendicular to the substrate 110. As an example, the substrate 110 may include a conductive substrate. The substrate 110 may be or may include an insulating substrate or a semiconductor substrate having an insulating layer formed on a surface thereof.
The lower electrode 120 may be arranged above the substrate 110. The lower electrode 120 may be positioned above the substrate 110 and below the oxide channel 140. The lower electrode 120 may be positioned in the vertical direction Z with respect to the substrate 110. The oxide channel 140 may function as a channel layer, e.g. as a channel layer of a transistor. The lower electrode 120 may include a metal material. The lower electrode 120 may include at least one selected from the group consisting of or including tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), antimony (Sb), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and magnesium (Mg). The lower electrode 120 may be in contact with, or in direct contact with the substrate 110, but may be electrically connected to the substrate 110 even if it is not in contact with the substrate 110.
The oxide channel 140 may be deposited in an ALD manner. The oxide channel 140 may be deposited in a plasma enhanced-atomic layer deposition (PE-ALD) manner. The oxide channel 140 may be selected from the group consisting of or including InGaZnO, ZnO, ZrInZnO, InZnO, InGaZnO4, ZnInO, ZnSnO, In2O3, Ga2O3, HfInZnO, GaInZnO, HfO2, SnO2, WO3, TiO2, Ta2O5, In2O3SnO2, MgnO2, ZnSnO3, ZnSnO4, CdZnO, CuAlO2, CuGaO2, Nb2O5, TiSrO3, zinc indium oxide (ZIO), indium gallium oxide (IGO), and a combination thereof. Alternatively or additionally, the oxide channel 140 may function as a channel layer and may have a band gap of 3.0 electron-volts (ev) or more.
As the ALD method is performed at a higher temperature than a sputtering process and uses a material having a high reactivity as a deposition material, other layers may be affected during the deposition of a target layer. For example, when forming the oxide channel 140 on the lower electrode 120 through the ALD method, the oxygen source of the oxide channel 140 may react to the lower electrode 120 adjacent thereto, and the interfacial resistance may increase.
The semiconductor device 100 according to an embodiment may include the buffer 130 between the lower electrode 120 and the oxide channel 140 to improve performance of the semiconductor device. For example, the buffer 130 may include silicide material or metal having lower reactivity with oxygen than an electrode material to oxygen, and the oxygen source may not pass through the buffer 130. Accordingly, the reaction between the lower electrode 120 and the oxygen source may be substantially prevented during the process of forming the oxide channel 140.
A metal oxide 190 may be arranged on the lower electrode 120. A metal included in the metal oxide 190 may be identical to a metal included in the lower electrode 120. For example, the metal oxide 190 may include at least one of W, Co, Ni, Fe, Ti, Mo, Cr, Zr, Hf, Nb, Ta, Ag, Au, Al, Cu, Sb, V, Ru, Pt, An, and Mg.
The metal oxide 190 may be formed by reacting a metal source on or in the lower electrode 120 or oxidizing a metal of the lower electrode 120 by heat treatment, etc. in the process of forming the oxide channel 140. The vertical direction (z-direction) level of the upper of the metal oxide 190 may be substantially equal to the vertical direction (z-direction) level of the upper surface of the lower electrode 120. The content of oxygen included in the metal oxide 190 may be changed towards an oxide channel 140 from the lower electrode 120. For example, the content of oxygen included in the metal oxide 190 may decrease as a distance to oxide channel 140 increases. An interface between the lower electrode 120 and the metal oxide 190 may be unclear. For example, the metal oxide 190 may be formed as a part of the lower electrode 120. The metal oxide 190 may be formed discontinuously or continuously on the lower electrode 120.
The buffer 130 may be positioned on the upper surface of the metal oxide 190. The buffer 130 may be positioned in the vertical direction z of the metal oxide 190. The oxide channel 140 may cover the entire upper surface of the buffer 130. The width of the oxide channel 140 (for example, the width in the x-axis direction as shown in
The buffer 130 may include a silicide material (e.g., WSix, RuSix, NiSix, or TiSix). Here, x may represent a number greater than 1 and less than 3. Alternatively or additionally, the buffer 130 may include a metal (e.g., Mo, Au, Pt, Rh, Ru, Ti, Ta, or Ir) that has a lower oxidation reactivity than the lower electrode 120. In some example embodiments, the thickness of the buffer 130 may be about 1 Angstrom to about 50 Angstroms. The buffer 130 may cover all or at least a part of the upper surface of the lower electrode 120. Here, the lower electrode 120 may be formed as or correspond to a bit line, and the buffer 130 may be provided along the lower electrode 120. Alternatively or additionally, for example, the width of the buffer 130 may be the same as the width of the lower electrode 120, the metal oxide 190.
The oxide channel 140 may be arranged on, in, or at least partially in or within the buffer 130. The oxide channel 140 may be in contact with the upper surface of the buffer 130. The oxide channel 140 may be located in the vertical direction Z with respect to the buffer 130. The oxide channel 140 may cover the entire upper surface of the buffer 130. For example, the width of the oxide channel 140 may be the same as the width of the buffer 130. The oxide channel 140 may extend in a direction in which the substrate 110, the lower electrode 120, and the buffer 130 are sequentially stacked. The width of the oxide channel 140 may be the same as the width of the lower electrode 120, the metal oxide 190, or the buffer 130.
The semiconductor device 100 according to an embodiment may have a proper thickness ratio among the lower electrode 120, the metal oxide 190, the buffer 130, and the oxide channel 140. As the metal oxide 190 has high resistance characteristics when its thickness is greater than or equal to a certain value, the characteristics of the semiconductor device 100 may be deteriorated. For example, the density of an on current flowing in the lower electrode 120 and the oxide channel 140 may decrease drastically. The thickness of the buffer 130 may control the thickness of the metal oxide 190. For example, the greater the thickness of the buffer 130 is, the thinner the thickness of the metal oxide 190 may be. As a great thickness of the buffer 130 leads to an increased size of the semiconductor device 100, the thickness of the buffer 130 may be up to one time the thickness of the oxide channel 140.
The thickness of the metal oxide 190 may be less than the thickness of the lower electrode 120. The thickness of the metal oxide 190 may be less than or equal to about 25%, less than or equal to about 20%, or less than or equal to about 18% of the thickness of the lower electrode 120, and may be greater than or equal to 1% of the thickness of the lower electrode 120.
The gate electrode 150 may be arranged to be spaced apart from the oxide channel 140. The gate electrode 150 may be arranged to face a part or all of the oxide channel 140. The gate electrode 150 may include an electrically conductive material. For example, the gate electrode 150 may include a metal and/or a metal compound. In this case, the gate insulation layer 160 may be arranged between the oxide channel 140 and the gate electrode 150 to electrically disconnect the oxide channel 140 with the gate electrode 150. The gate insulating layer 160 may include an insulating material. For example, the gate insulating layer 160 may include a dielectric. The width of the gate insulating layer 160 may be the same as the width of the gate electrode 150.
The upper electrode 170 may be arranged on the oxide channel 140. The upper electrode 170 may include a metal material. The upper electrode 170 may be located on the oxide channel 140 in a direction where the lower electrode 120, the metal oxide 190, the buffer 130, and the oxide channel 140 are sequentially stacked. The upper electrode 170 may be positioned in a vertical direction of the oxide channel 140. The lower electrode 120, the metal oxide 190, the buffer 130, the oxide channel 140, and the upper electrode 170 may be stacked in order in a direction perpendicular to the substrate 110 without intervention of other layers.
The mold insulator 180 may fill an empty space so that the lower electrode 120, the metal oxide 190, the buffer 130, the oxide channel 140, the upper electrode 170, the gate electrode 150, and the gate insulation layer 160 are fixed on the substrate 110. The mold insulator 180 may include an insulating material.
Each of the oxide channel 140, the gate electrode 150, and/or the gate insulating layer 160 may be vertically arranged on the substrate 110, and the semiconductor device 100 may have a 3D structure (e.g., a vertical channel structure). The longitudinal direction of the oxide channel 140 may be vertically arranged on the substrate 110. Here, when the lower electrode 120 is deposited first and then the oxide channel 140 is deposited on the upper surface of the lower electrode 120, the composition of the interface of the lower electrode 120 may be separated, and a Zn-rich composition may be caused. For example, the atomic percent of Zn in a metal contact part of the oxide channel 140 may be higher than the atomic percent of other metal components (for example, when the composition ratio of In, Ga, and Zn in the InGaZnO oxide is 1:1:1, the composition ratio of the metal contact part is 1:1:x, and x is a real number more than 1). The metal contact part may refer to the thickness of 0 nm to 2 nm from the contact interface of the oxide channel 140 in contact with the lower electrode 120 and/or the upper electrode 170. Accordingly, interface resistance of the lower electrode 120 may be increased, and/or device characteristics of the semiconductor device 100 may be deteriorated. However, by introducing the buffer 130 between the lower electrode 120 and the oxide channel 140, it is possible to suppress or at least partially suppress the separation of the interface composition of the lower electrode 120 and lower the interface resistance of the lower electrode 120. When the buffer 130 is introduced between the lower electrode 120 and the oxide channel 140, the atomic percent of In in the metal contact part of the oxide channel 140 may be more than the atomic percent of Zn in the metal contact part of the oxide channel 140. For example, based on a case where the composition ratio of In, Ga, and Zn in the InGaZnO oxide is 1:1:1, the composition ratio of the metal contact part may be y:1:1, and y may be a real number of 1 or more.
Referring to
In
Referring to
The gate electrode 450 may have a shape similar to that of the oxide channel 440 and may be arranged to be spaced apart from the oxide channel 440. For example, the gate electrode 450 may include a first part 450a parallel to the substrate 410, a second part 450b in the longitudinal direction which is bent and extended from the first portion 450a in a direction perpendicular to the first substrate 410, and a third part 450c which is bent and extended from the second part 450b in the opposite direction to the first part 450a. A gate insulating layer 460 may be provided between the oxide channel 440 and the gate electrode 450.
Since the buffer 430 is substantially the same as the buffer 130 and the metal oxide 490 is substantially the same as the metal oxide 190 described with reference to
Referring to
The oxide channel 540 may have a U-shaped cross-sectional shape. The oxide channel 540 may include a bottom part 543 in contact with the buffer 530, a first vertical extension part 541 extending in a direction perpendicular to the lower electrode 520 from one end of the bottom part 543, and a second vertical extension part 542 extending in a direction perpendicular to the lower electrode 520 from the other end of the bottom part 543. The first vertical extension part 541 and/or the second vertical extension part 542 in the longitudinal direction of the oxide channel 540 may be provided perpendicularly to the substrate.
A first gate electrode 551 may be spaced apart from the first vertical extension 541, and a second gate electrode 552 may be spaced apart from the second vertical extension 542. A first gate insulating layer 561 may be provided between the first vertical extension part 541 and the first gate electrode 551, and a second gate insulating layer 562 may be provided between the second vertical extension part 542 and the second gate electrode 552.
The first gate electrode 551 and/or the second gate electrode 552 may extend in a second horizontal direction (Y direction). The first gate electrode 551 and the second gate electrode 552 may be spaced apart from each other. The first gate electrode 551 and/or the second gate electrode 552 may constitute or correspond to a word line WL (cf.
An insulating liner 591 may be arranged between the first gate electrode 551 and the second gate electrode 552 spaced apart from each other. The insulating liner 591 may be conformally arranged on the side walls in which the first gate electrode 551 faces the second gate electrode 552, and/or the upper surface of the oxide channel 540. The insulating liner 591 may have an upper surface arranged on the same plane as the upper surfaces of the first gate electrode 551 and the second gate electrode 552. The insulating liner 591 may include, for example, silicon nitride. A buried insulating layer 592 may fill a space between the first gate electrode 551 and the second gate electrode 552 spaced apart from each other on the insulating liner 591. The buried insulating layer 592 may include, for example, silicon oxide. An upper insulating layer 593 may be arranged on the upper surfaces of the first gate electrode 551, the second gate electrode 552, and/or the buried insulating layer 592. The upper surface of the upper insulating layer 593 may be arranged at the same level as the upper surface of the mold insulator 580.
The upper electrode 570 may be arranged on the oxide channel 540. The upper electrode 570 may serve as or correspond to a landing pad. The upper electrode 570 may include a left upper electrode and a right upper electrode. The left upper electrode may be electrically connected to the first vertical extension 541. The right upper electrode may be electrically connected to the second vertical extension 542. The left upper electrode and the right upper electrode may not be electrically connected with each other. The upper electrode 570 may include an upper portion and a lower portion. The upper portion of the upper electrode 570 may be a portion of the upper electrode 570 arranged at a higher level than the upper surface of the mold insulator 580. The lower part of the upper electrode 570 may be a part of the upper electrode 570 arranged inside an upper electrode recess defined between the mold insulator 580 and the upper insulating layer 593. In various example embodiments, the upper part of the upper electrode 570 may have a first width w1 in a first horizontal direction (X), and the lower part of the upper electrode 570 may have a second width w2 smaller than the first width w1 in the first horizontal direction (X). The lower part of the upper electrode 570 may be arranged inside the upper electrode recess, and the upper part of the upper electrode 570 may have a bottom surface arranged on the upper surface of the mold insulator 580 and the upper surface of the upper insulating layer 593. Accordingly, the upper electrode 570 may have a T-shaped vertical cross-section. A bottom surface of the lower part of the upper electrode 570 may contact the upper portions of the surfaces of the first vertical extension part 541 and/or the second vertical extension part 542. Both sidewalls of the lower portion of the upper electrode 570 may be aligned with both sidewalls of the first vertical extension part 541 and the second vertical extension part 542. The bottom surface of the lower part of the upper electrode 570 may be arranged at a higher level than the upper surface of the first gate electrode 551 and/or the upper surface of the second gate electrode 552, and a part of the sidewall of the lower part of the upper electrode 570 may be covered by the first gate insulating layer 561 and/or the second gate insulating layer 562. An upper electrode insulating layer 594, which surrounds the upper electrode 570, may be arranged on the upper surfaces of the mold insulator 580 and the upper insulating layer 593. The semiconductor device 500 may have a vertical channel transistor (VCT) structure including a vertical channel region extending in the vertical direction (z) of the lower electrode 520.
Since the buffer 530 is substantially the same as the buffer 130 and the metal oxide 590 is substantially the same as the metal oxide 190 described with reference to
Referring to
When compared to
The first oxide channel 641 and the second oxide channel 642 may be positioned so that the longitudinal directions thereof are arranged in a direction (z direction) perpendicular to the substrate (not illustrated).
Referring to
Referring to
Next, a method of manufacturing a semiconductor device according to various example embodiments will be described with reference to
Referring to
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The gate electrode 1050 and/or the gate insulating layer 1060 may be etched toward the bottom of the openings to partially expose the upper surface of the oxide channel 1040.
Referring to
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The method of manufacturing a semiconductor device including a buffer according to an embodiment may provide the semiconductor including the buffer 1030 between the lower electrode 1020 and the oxide channel 1040 to improve performance of the semiconductor device. For example, the buffer 1030 may include silicide material or metal having lower reactivity with oxygen than an electrode material to oxygen, and the oxygen source may not pass through the buffer 1030. Accordingly, the reaction between the lower electrode 1020 and the oxygen source may be substantially prevented during the process of forming the oxide channel 1040.
The semiconductor device according to various example embodiments is suitable for application to an integrated circuit device having a high degree of integration because it has a micro size and excellent electrical performance.
The semiconductor device according to various example embodiments may constitute a transistor applied for a digital circuit or an analog circuit. In some embodiments, an example semiconductor device may be used as a high voltage transistor or a low voltage transistor. For example, a semiconductor device of various example embodiments may constitute or correspond to a high voltage transistor that constitutes or is included in a peripheral circuit of a flash memory device and an electrically erasable and programmable read only memory (EEPROM) device, which is a nonvolatile memory device operating at a high voltage. Alternatively or additionally, various example embodiments may constitute or correspond to a transistor included in an IC chip for a liquid crystal display (LCD), an IC chip used in an LED display device, or a micro LED display device, and the like.
Referring to
The CMOS inverter 1600 includes a CMOS transistor 1610. The CMOS transistor 1610 includes a PMOS transistor 1620 and an NMOS transistor 1630 connected between a power terminal Vdd and a ground terminal. The CMOS transistor 1610 may include a semiconductor device according to various example embodiments described above with reference to
The CMOS SRAM element 1700 includes a pair of driving transistors 1710. The pair of driving transistors 1710 include a PMOS transistor 1720 and an NMOS transistor 1730 connected between a power terminal Vdd and a ground terminal, respectively. The CMOS SRAM element 1700 may further include a pair of transmission transistors 1740. A source of each of the transmission transistors 1740 is cross-connected to a common node of the PMOS transistor 1720 and the NMOS transistor 1730 constituting each of the driving transistors 1710. A power terminal Vdd is connected to a source of the PMOS transistor 1720, and a ground terminal is connected to a source of the NMOS transistor 1730. A word line WL may be connected to a gate of each of a pair of transmission transistors 1740, and a bit line BL and an inverted bit line may be connected to drains of the pair of transmission transistors 740, respectively.
At least one of the driving transistor 1710 and the transmission transistor 1740 of the CMOS SRAM device 1700 may include a semiconductor device according to various example embodiments described above with reference to
The CMOS NAND circuit 1800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 1800 may include a semiconductor device according to various example embodiments described above with reference to
The electronic system 1900 includes a memory 1910 and a memory controller 1920. The memory controller 1920 may control the memory 1910 to read data from the memory 1910 and/or write data to the memory 1910, in response to a request from the host 1930. At least one of the memory 1910 and the memory controller 1920 may include a semiconductor device according to various example embodiments described above with reference to
The electronic system 2000 may configure a wireless communication device or a device capable of transmitting and/or receiving information under a wireless environment. The electronic system 2000 includes a controller 2010, an input/output device (I/O) 2020, a memory 2030, and a wireless interface 2040, which are interconnected through a bus 2050.
The controller 2010 may include at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input/output device 2020 may include at least one of a keypad, a keyboard, and a display. The memory 2030 may be used to store a command executed by the controller 2010. For example, the memory 2030 may be used to store user data. The electronic system 2000 may use the wireless interface 2040 to transmit/receive data through a wireless communication network. The wireless interface 2040 may include an antenna and/or a wireless transceiver. The electronic system 1000 may include a semiconductor device according to various example embodiments described above with reference to
The semiconductor device and/or a manufacturing method thereof according to various example embodiments may suppress a side reaction and an interface composition separation phenomenon induced during semiconductor deposition. In addition, improved contact characteristics may be provided, and ion degradation may be prevented or reduced in likelihood of occurrence.
The semiconductor device according to various example embodiments includes a buffer including a silicide material between an electrode and an oxide channel, thereby reducing or suppressing side reactions and/or interface composition separation induced during deposition of oxide semiconductor and providing improved contact properties. In the method of manufacturing a semiconductor device according to various example embodiments, a buffer including a silicide material may be formed between an electrode and an oxide channel.
Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.
It should be understood that various example embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. Example embodiments are not necessarily mutually exclusive with one another. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0129049 | Oct 2022 | KR | national |
| 10-2023-0131156 | Sep 2023 | KR | national |
