Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the accompanying drawings, in which:
Exemplary embodiments of the present invention and methods of accomplishing the same may be understood more readily by reference to the following detailed description of exemplary embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to
Referring to
A substrate or SOI (Silicon On Insulator) substrate made of one or more semiconductor materials selected from a group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP may be used as the semiconductor substrate 100. The material used to form the substrate 100, however, is not limited to these materials.
A PMOS transistor 120P is formed in each PMOS transistor region I, and an NMOS transistor 120N is formed in each NMOS transistor region II.
The PMOS transistor 120P includes a gate electrode 126 that is formed on a high-dielectric gate insulating film 121 formed on an SiGe channel region A between P-type source and drain regions 129P.
According to the exemplary embodiment of the present invention, since the SiGe channel region A is used in the PMOS transistor 120P, it is possible to improve the carrier mobility of the PMOS transistor and to reduce the threshold voltage Vth of the PMOS transistor.
The conduction band offset of SiGe is lower than that of Si by about 30 mV, and the valence band offset of SiGe is lower than that of Si by about 230 mV. Accordingly, since the SiGe channel region A is used in the PMOS transistor 120P, it is possible to improve the threshold voltage characteristic of the PMOS transistor 120P.
In this exemplary embodiment, the SiGe channel region A may be formed in an SiGe epitaxial layer 111, and the SiGe epitaxial layer 111 may be formed in a recess R of the semiconductor substrate 100, as shown in
In this exemplary embodiment, the recess R of the semiconductor substrate 100 may be formed to have a depth of about 100 to 350 Å, and the SiGe epitaxial layer 111 fills the recess R and may be formed to have a thickness of about 100 to 300 Å. Further, the Si capping film 113 is formed on the SiGe epitaxial layer 111 so as to have a thickness of about 5 to 50 Å.
A high-dielectric film may be used as the gate insulating film 121. In this exemplary embodiment, the high-dielectric film means a film that is made of a material having a dielectric constant higher than a silicon oxide film, and is a film that is made of a material generally having a dielectric constant of 10 or more. For example, an oxide film, an aluminate film, a silicate film, or the like that contains at least one of the metals such as Hf, Zr, Al, Ti, La, Y, Gd, and Ta may be used as the high-dielectric film. The gate insulating film 121 may have a single layer structure or multilayer structure.
The thickness of the gate insulating film 121 may be in the range of about 10 to 60 Å, and the type and thickness of the gate insulating film may be changed without departing from the scope and spirit of the present invention.
Although not shown in the drawing, when the high-dielectric film is formed on the semiconductor substrate 100 so as to be used as the gate insulating film 121, a predetermined interface film (not shown) is further provided between the semiconductor substrate 100 and the gate insulating film 121 that is made of a high-dielectric material. The interface film improves the quality of the interface between the semiconductor substrate 100 and the gate insulating film 121, thereby improving the carrier mobility.
The gate electrode 126 may have a structure in which an upper gate electrode 125 is laminated on a lower gate electrode 123, but the structure of the gate electrode 126 is not limited to the above-mentioned structure. The lower gate electrode 123 serves as a barrier that prevents gate depletion from occurring when the upper gate electrode 125 is directly formed on the high-dielectric gate insulating film 121 or prevents dopants from entering from the polysilicon. Accordingly, the lower gate electrode 123 can prevent positive bias temperature instability (PBTI) from deteriorating, and improve the characteristic of the semiconductor device, and improve the electrical characteristic and reliability of the semiconductor device.
The lower gate electrode 123 may be made of a material that can prevent the dopants from being diffused in the upper gate electrode 125, which is formed on the lower gate electrode 123, and can suppress charge trapping. That is, the lower gate electrode 123 may be made of metal, metal nitride, or metal silicon nitride serving as the above-mentioned material. Further, the upper gate electrode 125 may be formed of a polysilicon film, a silicide film, or a laminated film formed by laminating the polysilicon film and the silicide film. The upper gate electrode 125, however, is not limited thereto. For example, the lower gate electrode 123 may be made of metal nitride, and the upper gate electrode 125 may be formed of a polysilicon film. Specifically, the lower gate electrode 123 may be formed of a nitride film that contains at least one of W, Mo, Ti, Ta, Al, Hf, and Zr, or a nitride film that includes metal containing at least one of W, Mo, Ti, Ta, Al, Hf and Zr, and Si or Al.
The NMOS transistor 120N includes a gate electrode 126 formed on the high-dielectric gate insulating film 121 that is formed on a Si channel region B between N-type source and drain regions 129N.
When the Si channel region B is used in the NMOS transistor 120N, it is possible to suppress of the diffusion of N-type dopants, such as As, as compared to when the SiGe channel region is used in the NMOS transistor. As a result, it is possible to reduce the deterioration of a short channel as compared to when the SiGe channel region is used in the NMOS transistor. For this reason, according to the exemplary embodiment of the present invention, the Si channel region B is used in the NMOS transistor 120N unlike the PMOS transistor 120P. Further, when the SiGe channel region is used in the NMOS transistor 120N, the carrier mobility deteriorates with no effect on the threshold voltage. Accordingly, unlike the PMOS transistor 120P, even though the Si channel region B is used in the NMOS transistor 120N, the threshold voltage can be maintained at an optimum level and the carrier mobility does not deteriorate. For this reason, it is advantageous to use the Si channel region B in the NMOS transistor 120N in terms of the characteristic of the semiconductor device.
The gate insulating film 121 may be formed of a high-dielectric film, as in the above-described PMOS transistor 120P. Further, the gate electrode 126 is also the same as in the PMOS transistor 120P. When a polysilicon film is formed in each of the gate electrodes of the PMOS transistor 120P and the NMOS transistor 120M and the type of polysilicon accords with the type of transistor, it is possible to obtain an advantageous characteristic of the semiconductor device. The present invention is not limited thereto, however, and the type of polysilicon does not need to accord with the type of the transistor.
As described above, the semiconductor device according to an exemplary embodiment of the present invention uses different channel regions depending on the types of the transistors. Accordingly, it is possible to improve the threshold voltage characteristic, that is, to maintain the absolute values of the NMOS transistors and the PMOS transistors at the same level. Further, since the deterioration of the short channel is suppressed, it is possible to improve the characteristic and reliability of the semi conductor device.
Referring to
Hereinafter, an exemplary method of manufacturing the semiconductor device, which has been described with reference to
First, referring to
Each of the element isolation films 105 may be formed using a common STI (Shallow Trench Isolation) method. The method of forming the element isolation film, however, is not limited to the STI method. An insulating film, such as an HDP (High Density Plasma SiO2) oxide film or an USG (Undoped Silicate Glass) film, may be used as each of the element isolation films 105. The element isolation film 105, however, is not limited to the above-mentioned insulating film.
As shown in
The epitaxial blocking film 107 blocks a specific portion of the semiconductor substrate 100 in a selective epitaxy growth process so as to prevent an epitaxial layer from being formed at the specific portion on the semiconductor substrate 100. As long as the epitaxial blocking film 107 has an etching selectivity different from that of the element isolation film 105, there is no limitation in the type of the epitaxial blocking film 107 or a method of forming the epitaxial blocking film 107. In this exemplary embodiment, the epitaxial blocking film 107 may be an oxide film that is formed using an atomic layer deposition (ALD) method, a chemical vapor deposition method, or the like. The epitaxial blocking film 107 may be a silicon oxide film that is formed at a relatively low temperature by using the atomic layer deposition method. For example, the silicon oxide film to be used as the epitaxial blocking film 107 may be formed at a temperature of about 100 to 150° C. by using the atomic layer deposition method SiH4, SiH2Cl2, SiHCl3, SiCl4, Si(OC4H9)4, Si(OCH3)4, Si(OC2H5)4, or the like may be used as a silicon source gas. The silicon source gas, however, is not limited thereto. Further, for example, H2O, O2, O3, O radical, alcohol, H2O2 or the like may be used as an oxygen source gas. However, the oxygen source gas is not limited thereto.
The thickness of the epitaxial blocking film 107 may be in the range of about 30 to 300 Å, but is not limited thereto.
As shown in
A mask pattern 109, for example, a photoresist pattern, which covers the NMOS transistor region II and exposes the PMOS transistor region I to the outside, may be formed to selectively remove the epitaxial blocking film 107P formed in the PMOS transistor region I. The mask pattern 109 may be removed using an etching process or an ashing process after a process for selectively removing the epitaxial blocking film 107P.
As described above, because the epitaxial blocking film 107 is made of a material having an etching selectivity different from that of the element isolation film 105, it is possible to selectively remove the epitaxial blocking film 107 with no effect on the element isolation film 105. For example, a silicon oxide film, which is formed by the above-mentioned atomic layer deposition method, can be removed using a diluted hydrofluoric acid solution. In this case, there is no effect on the element isolation film 105.
Next, as shown in
Because the remaining epitaxial blocking film 107N can serve as an etch mask in the NMOS transistor region II, the recess R may be formed only in the PMOS transistor region I. The recess R may be formed by wet etching or dry etching that is used to selectively remove a part of the semiconductor substrate 100. A CDE (Chemical Dry Etching) may be used as the dry etching. For example, the CDE may be performed so that the amount of CF4 and O2 gas is adjusted to adjust the etching selectivity of the Si and SiO2.
The recess R may be formed on the upper surface of the semiconductor substrate 100 so as to have a depth d of about 100 to 350 Å.
Referring to
An SiGe channel region A for a PMOS transistor may be formed in the SiGe epitaxial layer 111. Because the epitaxial blocking film 107 remains in the NMOS transistor region II, an epitaxial layer is not formed in the NMOS transistor region II by a selective epitaxy process.
The selective epitaxy process for forming the SiGe epitaxial layer 111 may be performed at a temperature of about 500 to 900° C. and at a pressure of about 1 to 500 Torr, and may be appropriately adjusted without departing from the scope and spirit of the present invention. Further, SiH4, SiH2Cl2, SiHCl4, SiCl4, SiHxCly(x+y=4), Si(OC4H9)4, Si(OCH3)4, Si(OC2H5)4 or the like may be used as the silicon source gas, and GeH4, GeCl4, GeHxCly(x+y=4) or the like may be used as the Ge source gas. The silicon source gas and the Ge source gas, however, are not limited thereto. Furthermore, a gas such as HCl or Cl2 may be added to the source gases to improve the selective characteristic. When HCl or the like is added to the source gases, it is possible to achieve the selective epitaxy growth. In the selective epitaxy growth, an epitaxial layer is not formed on the element isolation film 105 or the epitaxial blocking film 107N that is formed of an oxide film or a nitride film, but is formed on the semiconductor substrate, that is, in the region where Si is exposed to the outside. In this case, a dopant gas may be added to the source gases so as to provide dopants to the epitaxial layer. As described above, when the SiGe epitaxial layer is formed, the dopants may be doped by an in-situ process. The present invention, however, is not limited thereto. That is, after the SiGe epitaxial layer is formed, the dopants may also be doped by an ex-situ process.
According to an exemplary embodiment of the present invention, the content of Ge in the SiGe epitaxial layer 111 may be in the range of about 10 to 40 at % in consideration of the characteristic of the PMOS transistor. Further, the thickness of the SiGe epitaxial layer 111 may be in the range of about 100 to 300 Å. The selective epitaxy process has been widely known in the art, and the kinds and amounts of each of the source gases or added gases may be determined in consideration of the composition of the SiGe epitaxial layer to be formed, and the content of the dopants therein.
Subsequently, an Si capping film 113 may be further formed on the SiGe epitaxial layer 111. The Si capping film 113 may be selectively formed only on the SiGe epitaxial layer 111 by the selective epitaxy process.
The selective epitaxy process for forming the Si capping film 113 may be performed at a temperature of about 500 to 1000° C. and at a pressure of about 1 to 500 Torr, and may be appropriately adjusted without departing from the scope and spirit of the present invention. SiH4, SiH2Cl2, SiHCl3, SiCl4, SiHxCly(x+y=4), Si(OC4H9)4, Si(OCH3)4, Si(OC2H5)4 or the like may be used as the silicon source gas. Furthermore, a gas such as HCl or Cl2 may be added to the source gas to improve the selective characteristic. When HCl is added to the source gases, it is possible to achieve the selective epitaxy growth in which an epitaxial layer is not formed on the element isolation film 105 or the epitaxial blocking film 107N that is formed of an oxide film or a nitride film. In this case, dopants for forming channels may be doped in the Si capping film 113. As described above, when the Si epitaxial layer is formed, the dopants may be doped by an in-situ process, however, the present invention is limited thereto. That is, after the Si epitaxial layer is formed, the dopants may also be doped by an ex-situ process.
After that, as shown in
The process for removing the epitaxial blocking film 107N remaining in the NMOS transistor region II is substantially the same as the process, which has been described with reference to
Subsequently, as shown in
The gate insulating film 121a may be formed by the deposition of the material of the gate insulating film in the ALD or CVD process. In this case, the thickness of the gate insulating film 121a may be in the range of about 10 to 60 Å. Further, when a high-dielectric film is formed for use as the gate insulating film 121a, an interface film (not shown) may be further provided between the semiconductor substrate 100 and the gate insulating film 121a. The interface film can prevent a reaction from occurring between the high-dielectric film and the semiconductor substrate 100. The semiconductor substrate is cleaned using ozone water containing ozone gases or ozone, so that the thickness of the interface film is 1.5 nm or less.
After the deposition of the gate insulating film 121a, post deposition annealing (PDA) is performed so as to density the thin film. In this case, the PDA may be performed under an atmosphere, which includes at least one of N2, NO, N2O, O2, and NH3 gases, at a temperature of about 750 to 1050° C. The PDA may be appropriately adjusted depending on the kind or thickness of the thin film.
As shown in
More specifically, as shown in
The P-type source and drain regions 129P are formed in the PMOS transistor region I and the N-type source and drain regions 129N are formed in the NMOS transistor region II. Accordingly, it is possible to completely form the PMOS transistor 120P and the NMOS transistor 120N, shown in
In the following description of the exemplary method of manufacturing the semiconductor device, a process for forming wiring lines through which electrical signals are input and output, a process for forming a passivation layer on a substrate, and a process for packaging the substrate may be further performed in accordance with processes widely known to those of ordinary skill in the art of the semiconductor device, so as to completely form the semiconductor device. These succeeding processes will be schematically described to avoid any ambiguous definition of the present invention.
Hereinafter, an exemplary method of manufacturing the semiconductor device shown in
Referring to
Subsequently, the Si capping film 213 may be formed on the SiGe epitaxial layer 211 by the selective epitaxy growth process.
After that, the gate electrode 126 shown in
Subsequently, the insulating spacer 127, the P-type source and drain regions 129P, and the N-type source and drain regions 129N are formed so as to completely form the semiconductor device shown in
Hereinafter, the following test will be described with reference to
Specifically, the NMOS transistors and the PMOS transistors are formed under the following conditions shown in the following Table 1, and the threshold voltages and the carrier mobilities are measured. An HfSiON film having a thickness of 30 Å is used as the gate insulating film. The ratio of width to length (W/L) is 1.0/1 μm, and a lower gate electrode formed of a TaN film and an upper gate electrode formed of a polysilicon film are laminated so as to be used as the gate electrode. An Si capping film is formed on the SiGe channel region.
Referring to
Referring to
As described above, it is advantageous to apply the SiGe channel region to the PMOS transistor and to apply the Si channel region to the NMOS transistor, in terms of the threshold voltage or carrier mobility.
Although the present invention has been described in connection with the exemplary embodiments of the present invention, it will be apparent to those skilled in the art that various modifications and changes may be made thereto without departing from the scope and spirit of the present invention. Therefore, it should be understood that the above-described exemplary embodiments are not limitative, but illustrative in all aspects.
As described above, according to the semiconductor device of exemplary embodiments of the present invention, the PMOS transistor is formed in the SiGe channel region, and the NMOS transistor is formed in the Si channel region. Accordingly, it is possible to improve the characteristics of the semiconductor device, such as the threshold voltage and carrier mobility thereof.
Number | Date | Country | Kind |
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10-2006-0075816 | Aug 2006 | KR | national |