This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2014-119846, filed on Jun. 10, 2014, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate to a semiconductor device and a method of manufacturing the same.
A field effect transistor using a nitride semiconductor material has excellent material properties such as a large band gap, a high electric field strength, and a high saturation velocity. For example, it is known that a two-dimensional electron gas (2DEG) layer of a high concentration and a high electron mobility is generated spontaneously on an interface between a gallium nitride (GaN) and an aluminum gallium nitride (AlGaN) due to polarization effect. At the interface, these layers are hetero-joined. An example of a transistor making use of 2DEGs due to this heterojunction is a heterojunction field effect transistor (HFET). The HFET shows great promise as a next-generation transistor such as a power control device and a switching device that need high-power, high-voltage, and high-temperature operations.
There are various structures of the HFET. Each of the structures has an appropriate application that can make use of its features. Among these structures, a vertical structure is suitable to reduce an on-resistance and to increase a breakdown voltage, and is suitable for a switching device or the like. However, even with the vertical structure, the on-resistance per unit area is increased as the area of a cell (cell pitch) is increased, which makes the HFET unsuitable for the switching application. It is desired not only to reduce the cell pitch, but also to exert an operation of an enhancement type while enabling both an excellent pinch-off and a high electron mobility that serve to reduce the on-resistance as well.
Embodiments will now be explained with reference to the accompanying drawings.
In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type, and a second semiconductor layer of a second conductivity type provided on the first semiconductor layer. The device further includes a third semiconductor layer of the first conductivity type or an intrinsic type provided on the second semiconductor layer, and a fourth semiconductor layer provided on the first semiconductor layer. The device further includes a fifth semiconductor layer of the second conductivity type provided on the fourth semiconductor layer, and a control electrode provided on the second semiconductor layer through an insulating layer and electrically connected to the fifth semiconductor layer.
The semiconductor device in
Furthermore, the semiconductor device in
Reference characters n, p, and i shown in
An example of the substrate 1 is a semiconductor substrate such as a silicon substrate.
The buffer layer 2 is formed on the substrate 1. An example of the buffer layer 2 is a laminated film that includes an AlN (aluminum nitride) layer, an AlGaN layer, a GaN layer, and the like. Alternatively, examples of the buffer layer 2 also include one in which carbon atoms are doped.
The first n type contact layer 3 is formed on the buffer layer 2, and is in contact with the drain electrode 14. An example of the first n type contact layer 3 is an n+ type GaN layer with an n type impurity doped at a relatively high concentration. An example of this n type impurity is a silicon (Si) atom. The first n type contact layer 3 is provided for reducing a contact resistance with the drain electrode 14.
The first electron transport layer 4 is formed on the first n type contact layer 3. An example of the first electron transport layer 4 is an GaN layer of the i type, and may be an n-type GaN layer with an n type impurity doped at a concentration lower than that of the first n type contact layer 3. The first electron transport layer 4 is in contact with the lower portion and the side portion of the first p type semiconductor layer 5.
The first p type semiconductor layer 5 is formed on the first electron transport layer 4. An example of the first p type semiconductor layer 5 is a p type GaN layer with a p type impurity doped. An example of this p type impurity is a magnesium (Mg) atom. The first p type semiconductor layer 5 is in contact with the lower portion and the side portion of the second n type contact layer 6. A portion of the first p type semiconductor layer 5 in the vicinity of the gate electrode 12 is sandwiched between the first electron transport layer 4 and the second n type contact layer 6, and functions as a channel of the transistor.
The second n type contact layer 6 is formed on the first p type semiconductor layer 5, and is in contact with the source electrode 13. An example of the second n type contact layer 6 is an n+ type or i type GaN layer.
The electron supply layer 7 is formed on the first electron transport layer 4. An example of the electron supply layer 7 is an i type AlGaN layer.
The second p type semiconductor layer 8 is formed on the electron supply layer 7, and is in contact with the gate electrode 12. An example of the second p type semiconductor layer 8 is a p type AlGaN layer. The second p type semiconductor layer 8 of the present embodiment has a function of raising the potential of a channel on a heterointerface between the first electron transport layer 4 and the electron supply layer 7.
The p type contact layer 9 is formed on the first p type semiconductor layer 5, and is in contact with the side portion of the second n type contact layer 6. An example of the p type contact layer 9 is a p+ type GaN layer with a p type impurity doped at a concentration higher than that of the first p type semiconductor layer 5. The p type contact layer 9 is a layer for reducing a potential difference between the source electrode 13 and the first p type semiconductor layer 5 by being connected with the source electrode 13 via the p type source layer 10 to fix the potential of the first p type semiconductor layer 5.
The p type source layer 10 is formed on the p type contact layer 9, and is a layer for being in contact with the source electrode 13. The p type source layer 10 is provided for reducing a contact resistance with the source electrode 13.
The gate insulator 11 is formed on the first p type semiconductor layer 5 and the second n type contact layer 6. An example of the gate insulator 11 is a silicon dioxide film.
The gate electrode 12 is formed on the first p type semiconductor layer 5 and the second n type contact layer 6 through the gate insulator 11, and is electrically connected to the second p type semiconductor layer 8. An example of the gate electrode 12 is a metal layer. An example of this metal layer is a laminated film that includes at least any one of a platinum (Pt) layer, a nickel (Ni) layer, and a gold (Au) layer. The gate electrode 12 has a shape extending in the Y direction.
The source electrode 13 is formed on the second n type contact layer 6 and the p type source layer 10, and is in contact with the upper portion of the second n type contact layer 6, and the upper portion and the side portion of the p type source layer 10. The source electrode 13 has a shape extending in the Y direction.
The drain electrode 14 is formed under the first n type contact layer 3, and is in contact with the lower portion of the first n type contact layer 3. The drain electrode 14 has a shape extending in the Y direction. The drain electrode 14 of the present embodiment is further in contact with the lower portion and the side portions of the substrate 1, and the side portions of the buffer layer 2.
The interlayer dielectric 15 is formed on the substrate 1 such that the vertical transistor is covered therewith. An example of the interlayer dielectric 15 is a silicon dioxide film.
The second p type semiconductor layer 8 of the present embodiment has a function of raising the potential of a channel on a heterointerface between the first electron transport layer 4 and the electron supply layer 7. Therefore, when the transistor of the present embodiment is off, an energy level of a conduction band of the heterointerface becomes higher than the Fermi level thereof, and 2DEG in the channel is depleted. Therefore, the transistor of the present embodiment exerts an operation of an enhancement type in which it is brought into an off state when a gate voltage is not applied thereto.
On the other hand, when the transistor of the present embodiment is turned on, the upper surface of the first p type semiconductor layer 5 below the gate electrode 12 is channelized to be brought into a conduction state. Consequently, as shown by an arrow A, electrons flow from the second n type contact layer 6 to the first electron transport layer 4 via the first p type semiconductor layer 5. At the same time, positive holes are led from the second p type semiconductor layer 8 to the heterointerface as shown by arrows B, which generates electrons on the heterointerface. Consequently, electrons flow from the first electron transport layer 4 to the drain electrode 14.
In addition, the transistor of the present embodiment has a structure in which the source electrode 13 is disposed only on one side of the gate electrode 12. In addition, the first p type semiconductor layer 5 of the present embodiment pinches off the channel, thereby having a function as a barrier layer. According to the present embodiment, by disposing the source electrode 13 only on one side of the gate electrode 12, it is possible to pinch off the channel and to enhance the electron mobility of the transistor even if a bias voltage is zero. The cell structure of the present embodiment can have a shape such as a polygon, circle, and irregular shape.
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Subsequently, the interlayer dielectric 15 is formed on the substrate 1. Furthermore, various interlayer dielectrics, interconnect layers, and the like are formed on the substrate 1. In such a manner, the semiconductor device of the first embodiment can be manufactured.
As described above, the semiconductor device of the present embodiment includes the second n type contact layer 6 on the first electron transport layer 4 through the first p type semiconductor layer 5, and the second p type semiconductor layer 8 on the first electron transport layer 4 through the electron supply layer 7. Therefore, according to the present embodiment, it is possible to deplete a 2DEG layer on an interface between the first electron transport layer 4 and the electron supply layer 7, which consequently enables the vertical transistor using a nitride semiconductor material to exert an operation of an enhancement type.
The electron supply layer 7 of the present embodiment is divided into a first portion 7a and a second portion 7b. The first portion 7a is an example of the fourth semiconductor layer. The second portion 7b is an example of a sixth semiconductor layer. Furthermore, in the present embodiment, the second n type contact layer 6 of the first embodiment is replaced with a second electron transport layer 16. An example of the second electron transport layer 16 is an i type GaN layer. The second electron transport layer 16 is an example of the third semiconductor layer.
The first portion 7a is formed on the first electron transport layer 4. An example of the first portion 7a is an i type AlGaN layer. The second p type semiconductor layer 8 is formed on the first portion 7a.
The second portion 7b is formed on the second electron transport layer 16. An example of the second portion 7b is, as with the first portion 7a, an i type AlGaN layer. The gate insulator 11 is formed on the first p type semiconductor layer 5 and the second portion 7b, and is interposed between the first portion 7a and the second portion 7b. The gate insulator 11 is also in contact with a side portion of the second p type semiconductor layer 8. The gate electrode 12 is formed on the first p type semiconductor layer 5 and the second portion 7b via the gate insulator 11. The gate electrode 12 is formed also on the second p type semiconductor layer 8, and is electrically connected to the second p type semiconductor layer 8. The source electrode 13 is formed on the second portion 7b and the p type source layers 10, and is in contact with the upper portion of the second portion 7b, and the upper portions and the side portions of the p type source layers 10.
In addition, the semiconductor device of the present embodiment includes, as shown in
The second p type semiconductor layer 8 of the present embodiment has a function of raising the potential of a channel on a heterointerface between the first electron transport layer 4 and the first portion 7a. Therefore, when the transistor of the present embodiment is off, an energy level of a conduction band in this heterointerface becomes higher than the Fermi level thereof, and a 2DEG in the channel is depleted. Therefore, the transistor of the present embodiment exerts the operation of the enhancement type.
On the other hand, when the transistor of the present embodiment is turned on, the upper surface of the first p type semiconductor layer 5 below the gate electrode 12 is channelized and brought into a conduction state. Consequently, as shown by an arrow A, electrons flow from the second electron transport layer 16 to the first electron transport layer 4 via the first p type semiconductor layer 5. At the same time, positive holes are led from the second p type semiconductor layer 8 to the above-described heterointerface as shown by arrows B, which generates electrons on the above-described heterointerface. Consequently, electrons flow from the first electron transport layer 4 to the drain electrode 14.
In addition, in the present embodiment, as shown by reference character C, electrons (2DEG) are generated also on a heterointerface between the second electron transport layer 16 and the second portion 7b. These electrons serve as carriers of channel current flowing as shown by the arrow A. Therefore, according to the present embodiment, it is possible to reduce the on-resistance of the transistor more compared with the first embodiment.
First, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, the processes of
The electron supply layer 7 of the present embodiment is, as with the second embodiment, divided into the first portion 7a and the second portion 7b. In addition, the second p type semiconductor layer 8 of the present embodiment is divided into a third portion 8a, a fourth portion 8b, and a fifth portion 8c. The third portion 8a is an example of the fifth semiconductor layer. The fourth portion 8b is an example of a seventh semiconductor layer.
The third portion 8a is formed on the first portion 7a, and is in contact with the gate electrode 12. An example of the third portion 8a is a p type AlGaN layer. The third portion 8a of the present embodiment has a function of raising the potential of a channel on a heterointerface between the first electron transport layer 4 and the first portion 7a.
The fourth portion 8b is formed on the second portion 7b, and is in contact with the gate electrode 12. An example of the fourth portion 8b is, as with the third portion 8a, a p type AlGaN layer. The fourth portion 8b of the present embodiment has a function of raising the potential of a channel on a heterointerface between the second electron transport layer 16 and the second portion 7b.
The fifth portion 8c is formed the second portion 7b, and is in contact with the source electrode 13. An example of the fifth portion 8c is, as with the third and fourth portions 8a and 8b, a p type AlGaN layer.
The gate insulator 11 is formed on the first p type semiconductor layer 5, and is interposed between the first portion 7a and the second portion 7b. The gate electrode 12 is formed on the first p type semiconductor layer 5 via the gate insulator 11, and is electrically connected to the third and fourth portions 8a and 8b. The source electrode 13 is formed on the second portion 7b and the p type source layers 10 (not shown), and is in contact with the upper portion of the second portion 7b, the side portions of the fifth portion 8c, and the upper portions and the side portions of the p type source layers 10. The shapes and dispositions of the p type contact layers 9 and the p type source layers 10 of the present embodiment are the same as those of the second embodiment.
The third portion 8a of the present embodiment has a function of raising the potential of a channel on a heterointerface between the first electron transport layer 4 and the first portion 7a. Therefore, when the transistor of the present embodiment is off, an energy level of a conduction band of this heterointerface becomes higher than the Fermi level thereof, and 2DEG in the channel is depleted. This applies also to the heterointerface between the second electron transport layer 16 and the second portion 7b. Consequently, the transistor of the present embodiment exerts the operation of the enhancement type.
On the other hand, when the transistor of the present embodiment is turned on, the upper surface of the first p type semiconductor layer 5 below the gate electrode 12 is channelized to be brought into a conduction state. At the same time, as shown by arrows B and D, positive holes are led from the third and fourth portions 8a and 8b to both the above-described heterointerfaces, which generates electrons on these heterointerfaces. Then, these electrons serve as carriers of current flowing as shown by an arrow A.
In the present embodiment, the 2DEG in the channel is depleted by not only the third portion 8a but also the fourth portion 8b. Therefore, according to the present embodiment, it is possible to enhance the pinch-off property of the transistor as compared with the second embodiment.
First, the processes of
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, the processes of
The substrate 1 of the first to third embodiments may be a GaN substrate instead of a silicon substrate. Using a GaN substrate as the substrate 1 offers an advantage in that there is a small difference of lattice constants between the substrate 1 and a nitride semiconductor layer. Therefore, in this case, the opening H3 does not need to be formed on the back surface of the substrate 1, and the buffer layer 2 is also not necessary.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2014-119846 | Jun 2014 | JP | national |