Claims
- 1. A method of manufacturing a semiconductor device, the method comprisinga first film forming step of successively forming, on a semiconductor substrate, a first insulating film having a relatively large thickness and a polysilicon film; a first patterning step of patterning the polysilicon film and the first insulating film to form a first-layer gate insulating film of a flash memory and a dummy gate insulating film, each being composed of the first insulating film, and to form a floating gate electrode of the flash memory and a dummy gate electrode, each being composed of the polysilicon film; a sidewall forming step of forming sidewalls on each of the floating gate electrode and the dummy gate electrode; an insulating film removing step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate, removing the portions of the interlayer insulating film overlying the floating gate electrode and the dummy gate electrode, and thereby exposing the floating gate electrode and the dummy gate electrode; an etching step of forming, on the interlayer insulating film, a second insulating film covering the floating gate electrode and exposing the dummy gate electrode, performing etching by using the second insulating film to remove the dummy gate electrode and the dummy gate insulating film, and thereby forming a depressed portion internally of the sidewalls of the dummy gate electrode; a second film forming step of successively forming, over the entire surface of the semiconductor substrate, a third insulating film having a relatively small thickness and a metal film such that the depressed portion is filled therewith; and a second patterning step of patterning the second insulating film, the third insulating film, and the metal film to form a second-layer gate insulating film of the flash memory composed of the second and third insulating films, a gate insulating film of a FET composed of the third insulating film, a control electrode of the flash memory composed of the metal film, and a gate electrode of the FET composed of the metal film.
- 2. The method of claim 1, wherein the etching step includes the step of removing the dummy gate electrode and the dummy gate insulating film by wet etching.
- 3. The method of claim 1, whereinthe first patterning step includes the step of patterning the polysilicon film and the first insulating film to form a capacitor insulating film composed of the first insulating film and a capacitor lower electrode composed of the polysilicon film and the second patterning step includes the step of patterning the second insulating film, the third insulating film, and the metal film to form a capacitor insulating film composed of the second and third insulating films and a capacitor upper electrode composed of the metal film.
- 4. A method of manufacturing a semiconductor device, the method comprising:a first film forming step of successively forming, on a semiconductor substrate, a first insulating film having a relatively large thickness and a multilayer structure being composed of a lower-layer polysilicon film and an upper-layer metal film of a refractory metal or a compound of a refractory metal and a patterning step of patterning the multilayer structure and the first insulating film to form a first gate insulating film, each being composed of the first insulating film, and to form a first gate electrode of the first FET and a dummy gate electrode, each being composed of the multilayer structure; a sidewall forming step of forming sidewall on each of the first gate electrode and the dummy gate electrode; an insulating film removing step of depositing an interlayer insulating film over the entire surface of the semiconductor substrate, removing the portion of the interlayer insulating film overlying the first gate electrode and the dummy gate electrode, and thereby exposing the first gate electrode and the dummy gate electrode; an etching step of forming, on the interlayer insulating film, a mask pattern covering the first gate electrode and exposing the dummy gate electrode, performing etching by using the mark pattern to remove the dummy gate electrode and the dummy gate insulating film, and thereby forming a depressed portion internally portion internally of the sidewalls of the dummy gate electrode; a second film forming step of successively forming, over the entire surface of the semiconductor substrate, a second insulating film having a relatively small thickness and a metal film such that the depressed portion is filled therewith; and a film removing step of removing the mark pattern and the portion of the second insulating film and the metal film located externally of the depressed portion and thereby forming a second gate insulating film and a second FET composed of the second insulating film and a second gate electrode of the second FET composed of the metal film.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-370113 |
Dec 1998 |
JP |
|
Parent Case Info
This application is a division of application Ser. No. 09/433,221, filed Nov. 4, 1999.
US Referenced Citations (5)
Number |
Name |
Date |
Kind |
5960270 |
Misra et al. |
Sep 1999 |
A |
6054355 |
Inumiya et al. |
Apr 2000 |
A |
6184093 |
Tsunashima et al. |
Feb 2001 |
B1 |
6228714 |
Choi |
May 2001 |
B1 |
6333223 |
Moriwaki et al. |
Dec 2001 |
B1 |
Foreign Referenced Citations (9)
Number |
Date |
Country |
03-046267 |
Feb 1991 |
JP |
04-162771 |
Jun 1992 |
JP |
08-107154 |
Apr 1996 |
JP |
09-148449 |
Jun 1997 |
JP |
09-232443 |
Sep 1997 |
JP |
09-293862 |
Nov 1997 |
JP |
10-189966 |
Jul 1998 |
JP |
11-074368 |
Mar 1999 |
JP |
11-126829 |
May 1999 |
JP |
Non-Patent Literature Citations (2)
Entry |
A. Chatterjee, et al., “CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator”, p, 777, 1998. |
Atsushi Yagishita et al., “High Performance Metal Gate MOSFETs Fabricated by CMP for 0.1um Regime” p. 785, 1998. |