Patent Application
20210134989
The present application claims priority to GB Patent Application No. 1915863.1 filed on 31 Oct. 2019. The entirety of this application is hereby incorporated by reference for all purposes.
The invention relates to the field of power semiconductor devices. Power semiconductor devices that are able to withstand a blocking voltage of several hundred Volts at high current rating are typically implemented as vertical or lateral structures, wherein the semiconductor wafer is based for example on a semiconducting material such as silicon (Si) or silicon carbide (SiC) or diamond or gallium oxide (Ga2O3) or gallium nitride (GaN) or zinc oxide (ZnO). More particularly, this invention relates to a method of manufacturing a power semiconductor device.
The basic approach to manufacture such a design is to implant both the N-type enhancement region (10) and P-type well region (9) through an opening in the gate electrode, followed by separate diffusion/activation processes for each implant. In a planar cell, the distance (92) in the lateral direction between the edge of the gate electrode (11) and the end of the P-well region (10) is normally around 70-80% of the diffusion depth in the vertical direction (91) of the P-well region (10), given by the P-type dopant (normally Boron) diffusion rates in the silicon material. This diffusion ratio is the same for the enhanced planar cell that makes simultaneous use of both N-type dopants in region (10), and P-type dopants in region (9).
In such a state-of-the-art enhanced planar MOS cell design, the vertical depth (93) is important for establishing a good voltage blocking capability, while the lateral distance (94) is needed for lowering the on-state losses. Hence, to obtain an improved trade-off, a shorter lateral length (94) resulting in a shorter channel and higher enhancement will be advantageous, while keeping the same vertical depth (93). In other words, a lateral distance (94) which is less than 70% of the vertical depth (93) is required. This can be achieved, but with the addition of more complex, costly processes, which are not self-aligned.
It is thus desirable to find a new planar MOS cell design that can still benefit from the enhanced layer concept, while enabling simple process steps and results in lower conduction/on-state losses.
It may be an object of the present invention to provide a power semiconductor device with reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking capability, and good controllability such as an Insulated Gate Bipolar Transistor (IGBT) with improved electrical characteristics.
These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent claims.
The problem is solved by the semiconductor device with the characteristics of claim 1.
The inventive power semiconductor device has layers of different conductivity types, which layers are arranged between an emitter electrode on an emitter side and a collector electrode on a collector side, which can be arranged opposite of the emitter side in the case of a vertical power semiconductor, but can also be arranged on the same emitter side in the case of lateral power semiconductors. The layers comprise, at a minimum:
The inventive semiconductor device improves a planar MOS cell in order to gain the advantages of using an advanced enhancement layer in terms of reduced on-state losses, low drainage of holes, stable gate parameters, improved blocking and good controllability.
An exemplary embodiment provides a method of manufacturing a power semiconductor device. The exemplary method includes: forming a first oxide layer on the emitter side of a substrate of a first conductivity type; forming a gate electrode layer with at least one opening on the emitter side on top of the first oxide layer; implanting a first dopant of the first conductivity type into the substrate on the emitter side using the formed gate electrode layer as a mask; diffusing the first dopant into the substrate; introducing a spacer at the edges of the gate electrode layer after the diffusion of the first dopant of the first conductivity type, which spacer can be formed with a dielectric layer such as silicon oxide, silicon nitride or other methods known to experts in the field; implanting a second dopant of a second conductivity type into the substrate on the emitter side; and diffusing the second dopant into the substrate.
The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (very good control of the width of the spacer can be achieved) with the potential of applying enhanced layer structures. The inventive design is suitable for full or part stripes but can also be implemented in cellular designs.
The inventive design is also suitable for reverse conducting structures, and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide (SiC). In particular, the use of a highly doped region of first conductivity type, manufactured, as per the embodiments of this invention, adjacent to the MOS channel, can be very beneficial in reducing the voltage drop in conduction mode for SiC MOSFET semiconductors.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings.
The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:
The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e. g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein.
In this specification, N-doped is referred to as first conductivity type while P-doped is referred to as second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be P-doped and the second conductivity type can be N-doped.
Specific embodiments described in this specification pertain to, without being limited thereto, insulated gate bipolar semiconductor devices.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. “between” versus “directly between”, “adjacent” versus “directly adjacent,” etc.).
A first exemplary embodiment of a power semiconductor device 200 in form of a punch through insulated gate bipolar transistor (IGBT) with a four-layer structure (pnpn) is shown as cross section representation in
An additional P-doped first base layer (9) is arranged between the drift layer (4) and the emitter electrode (3), and a second P-doped base layer (8) is arranged between the first base layer (9) and the emitter electrode (3), which second base layer (8) is in direct electrical contact to the emitter electrode (3), and has a higher doping concentration than the first base layer (9). An N-doped source region (7) is arranged at the emitter side (31) embedded into the first base layer (9), and contacts the emitter electrode (3), which source region has a higher doping concentration than the drift layer (4). The second base layer (8) extends perpendicularly deeper than the source region (7).
An advanced enhancement layer (10) of first conductivity type is arranged in the drift layer (4), between the drift layer and the first base (9), in such a manner that the first base layer (9) is embedded in the enhancement layer. The doping concentration of the enhancement layer is larger than the doping concentration of the drift layer (4), but significantly lower than the doping concentration of the source region (7). Main gate electrodes (11) are arranged on the surface of the emitter side (31), and are separated from the drift layer (4) by an electrically insulated layer (12). A lateral MOS channel (not shown) is formable between the emitter electrode (3), the source region (7), the first base layer (9) and the drift layer (4) when positive voltage is applied on the gate electrodes (11). The longitudinal direction of the main gate electrodes (11) is along a first horizontal direction which can be specific to a geometric axis in the starting material or can be randomly selected.
According to a first embodiment, the advanced enhancement layer (10) is formed in such a manner that the vertical maximum depth (95) of the first base layer (9), defined as the maximum distance from the surface of the emitter side to the junction depth between the first base layer and the enhancement layer (10), is substantially the same as the previous maximum depth when using a state-of-the-art enhancement layer. This ensures the blocking capability of the device is largely unchanged. However, the lateral length (96), defined as the distance from the edge of the gate electrode to the junction between the first base layer and the enhancement layer (on the emitter surface), is reduced compared to the same length when using a state-of-the-art enhancement layer. Consequently, the lateral MOS channel length is reduced, and the conduction losses are smaller than with prior art designs.
Further, an interlayer dielectric (13) electrically insulates the emitter electrode (3) from the gate electrodes (11) and may include by way of example one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass, for example BSG (boron silicate glass), PSG (phosphorus silicate glass) or BPSG (boron phosphorus silicate glass).
In a first embodiment, a P-doped collector layer (6) is arranged on the collector side (2) in direct electrical contact to the collector electrode (2) and a buffer layer (5) is arranged between the collector layer (6) and the drift region (4). Layers (5) and (6) can also be omitted in other embodiments (i.e. unipolar MOSFET device, non-punch-through power semiconductor devices).
The manufacturing method for a power semiconductor according to the first embodiment includes the following steps:
The manufacturing method for a power semiconductor according to the second embodiment includes the following steps:
The advanced enhancement layer (10) is formed of dopants of first conductivity type, preferably Phosphorous ions. The dopants are preferably implanted with an energy of 20-100 keV and/or a dose of 5×1012/cm2 to 5×1013/cm2. The dopants are driven into a maximum depth between 2 μm and 8 μm, in particular between 2 and 6 μm and in particular between 2 and 4 μm. With this enhancement layer, the conduction losses of the semiconductor device are improved.
The second dopants of second conductivity type are implanted into the substrate (4) using the structured gate electrode layer with its opening as a mask. The second dopants are preferably boron ions. The second dopants are preferably implanted with an energy of 20-100 keV and/or a dose of 5×1013/cm2 to 3×1014/cm2. The second dopants are driven into a maximum depth between 1 μm and 6 μm, in particular between 1 and 3 μm and in particular between 1 and 2 μm. The second dopants are not only driven into the substrate (4) in a direction perpendicular to the surface, but they are spread out laterally.
The third dopants of first conductivity type are is implanted into the substrate (4) using the structured gate electrode layer with its opening as a mask. The third dopants are preferably Phosphorous or Arsenic preferably Arsenic ions. The third dopants are preferably implanted with an energy of 80-160 keV and/or a dose of 1×1015/cm2 to 1×1016/cm2. The third dopants are driven into a maximum depth between 0.5 μm and 1.5 μm, and are mainly driven into the substrate (4) in a direction perpendicular to the surface, but they are only slightly spread out laterally to form the critical source region under the gate oxide (12).
Because the second dopant implant (70) is made after the spacer (15) is formed, a different distance (96) is provided between the edge of the gate electrode and the end of the first base layer (9), compared to state-of-the-art enhancement layer designs. Subsequent to diffusing the first base layer (9), a shorter lateral MOS channel is thus obtained when compared to the corresponding vertical depth (95) of the same first base layer (9). The condition that the lateral distance (96) represents less than 70% of the vertical distance of interest (95) is fulfilled with this design. Without providing the spacer (15), any effort to reduce the distance (96) and thus the MOS channel length would rely on increasing the dose of the first dopant implant (60), or on reducing the diffusion time of the second dopants. In either case, the vertical depth (95) would then be also substantially modified (i.e. shortened) which will drastically reduce the voltage blocking capability of the power semiconductor.
The spacer (15) can be formed with a dielectric layer such as silicon oxide, silicon nitride or other methods known to experts in the field. Depending on the manufacturing method used, the width (16) of the spacer layer (15) can be specifically controlled to very high resolution, even below 100 nm offering a precise control over the characteristics of the lateral MOS channel.
The inventive design is also suitable for a reverse conducting semiconductor device by introducing N-type dopants at the collector side to form the shorts (17) in the P-type collector layer (6), and producing an internal anti-parallel diode structure. This is illustrated in
In a fourth embodiment, it is possible to apply the same spacer concept to manufacture a cell structure that contains both planar gate electrodes (11) and trench gate electrodes (11), electrically insulated from the drift layer (4) by the insulating layers (12) and (12′) respectively. The advantage of such a planar trench structure resides in achieving an improved minority carrier concentration on the emitter side (31).
According to another embodiment, the planar gate structures (11) can also have a pattern like arrangement on a top view of the surface of the emitter side (31) for example squares, hexagons, octagons or other regular polygons.
It is possible to apply the invention to a method for the manufacturing of semiconductor devices, in which the conductivity type of all layers is reversed, i.e. with a lightly p doped substrate, etc.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1915864.1 | Oct 2019 | GB | national |
