Semiconductor Device and Method of Stabilizing Heat Spreader on Semiconductor Package

Abstract

A semiconductor device has an electrical component and heat sink disposed over the electrical component. A portion of the heat sink extends at least partially down a side surface of the electrical component to prevent lateral movement of the heat sink with respect to the semiconductor die. Alternatively, a portion of the heat sink extends at least partially below a surface of the electrical component. The heat sink can have an angled side, extension, or indentation to stabilize the heat sink on the electrical component to prevent rotation or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components or create defects on the PCB. The portion of the heat sink extending at least partially down does so on at least two side surfaces of the electrical component. The electrical component can be a flipchip semiconductor die.

Description

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of stabilizing a heat spreader or heat sink on a semiconductor die or package.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, photo-electric, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices are susceptible to heat from operation of the semiconductor die. Some semiconductor die, such as microprocessor, operate at a high clock frequency and generate heat from rapid transistor switching. Other semiconductor devices, such as a power MOSFET, generate heat by conducting significant current. FIG. 1a shows a conventional semiconductor die or package 10. In many applications, thermal interface layer (TIM) layer 12 is deposited over surface 14 of semiconductor die or package 10, and heat sink 18 is disposed over the TIM layer to dissipate heat. Ideally, the rectangular heat sink 18 is centered and squarely aligned with the rectangular semiconductor die 10, i.e., each side of heat sink is parallel with the corresponding side of the semiconductor die with equal distance between each side of the heat sink and each corresponding side of the semiconductor die, as shown in FIG. 1b. The heat sink alignment is particularly important when the heat sink is a similar size as the semiconductor die.

The heat sink is known to move or shift in position relative to the semiconductor die, for example during the curing process to bond the heat sink to the die. The heat sink may rotate off square alignment or shift position in the lateral direction from the semiconductor die, as shown in FIG. 1c. In such case, the sides of the rectangular heat sink are no longer parallel with the corresponding sides of the rectangular semiconductor die and there is no longer equal distance between each side of the heat sink and each corresponding side of the semiconductor die. In other words, the heat sink is askew with respect to and no longer aligned over the footprint of the semiconductor die.

The semiconductor die is commonly placed on a PCB to interact with other electrical components. The semiconductor die and heat sink are positioned close to the other electrical components on the PCB to optimize component density and overall functionality. Any misalignment between the heat sink and semiconductor die, i.e., when the heat sink rotates off square alignment or shifts position in the lateral direction from the semiconductor die, can cause the heat sink to extend beyond its intended position relative to the footprint of the semiconductor die and may contact adjacent electrical components. Edges 18a and 18b of heat sink 18 are misaligned and may contact adjacent components of the PCB. Such contact is considered a PCB defect due to the potential for short circuits and component damage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1a-1c illustrate a conventional semiconductor die and heat sink aligned and misaligned;

FIGS. 2a-2c illustrate a semiconductor wafer with a plurality of semiconductor die separated by a saw street;

FIGS. 3a-3f illustrate a process of mounting a heat sink with extensions to a semiconductor die or package;

FIGS. 4a-4e illustrate a process of mounting a heat sink with angled sides to a semiconductor die or package;

FIGS. 5a-5f illustrate a process of mounting a heat sink with indentations to a semiconductor die or package; and

FIG. 6 illustrates a printed circuit board (PCB) with different types of packages mounted to a surface of the PCB.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG. 2a shows a semiconductor wafer 100 with a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components 104 is formed on wafer 100 separated by a non-active, inter-die wafer area or saw street 106. Saw street 106 provides cutting areas to singulate semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

FIG. 2b shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface 110 to implement analog circuits or digital circuits, such as digital signal processor (DSP), application specific integrated circuits (ASIC), memory, or other signal processing circuit. Semiconductor die 104 may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 112 operates as contact pads electrically connected to the circuits on active surface 110.

An electrically conductive bump material is deposited over conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, bump 114 is formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesive layer. Bump 114 can also be compression bonded or thermocompression bonded to conductive layer 112. Bump 114 represents one type of interconnect structure that can be formed over conductive layer 112. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

In FIG. 2c, semiconductor wafer 100 is singulated through saw street 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. The individual semiconductor die 104 can be inspected and electrically tested for identification of KGD post singulation. In one embodiment, semiconductor die 104 is a flipchip semiconductor die.

In FIG. 3a, thermal interface material (TIM) 120 is deposited on back surface 108 of electrical component 121. In one embodiment, electrical component 121 is semiconductor die 104 from FIG. 2c. TIM 120 covers substantially an entire surface area of back surface 108 of semiconductor die 104.

In FIG. 3b, heat sink or heat spreader 122 is positioned over TIM 120 and back surface 108 of electrical component 121. Heat sink 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Heat sink 122 includes extensions or tabs 124 extending perpendicular with respect to surface 126 of the heat sink. Extensions 124 are cut from corners 136 of heat sink 122 and bent downward at 90 degrees with respect to surface 126. Extensions 124 have a flat face extending downward to contact or otherwise reside outside of side surface 132 of electrical component 121. The bottom view of heat sink 122 in FIG. 3c shows extensions 124 at corners 136 of the heat sink leaving internal area 130. Heat sink 122 will be fixed in position relative to electrical component 121 by nature of extensions 124 to prevent any lateral movement of the heat sink relative to the electrical component. FIG. 3d is a perspective view of surface 126 of heat sink 122 with extensions 124 at corners 136. FIG. 3e illustrates heat sink 122 mounted to back surface 108 of semiconductor die 104.

As discussed in the background, it would be undesirable for heat sink 122 to move in position relative to semiconductor die 104, for example during the curing process of TIM 120 to bond the heat sink to the die. The sides of heat sink 122 should remain parallel to the sides of semiconductor die 104. If heat sink 122 should rotate off square alignment or shift position in the lateral direction from semiconductor die 104, the sides of the rectangular heat sink would no longer parallel with the corresponding sides of the rectangular semiconductor die with equal distance between each side of the heat sink and each side of the semiconductor die, as shown in FIG. 1c. In other words, heat sink 122 would be askew with respect to and no longer align over the footprint of semiconductor die 104.

In particular and toward this goal, extensions 124 extend at least partially down side surface 132 of electrical component 121 to hold the electrical component within internal area 130. In another perspective, extensions 124 extend at least partially below surface 108 of electrical component 121. Extensions 124 extending at least partially down side surface 132, or at least partially below surface 108, hold heat sink 122 in place relative to semiconductor die 104 to prevent the heat sink from rotating or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components. Extensions 124 of heat sink 122 operate as anchor points to electrical component 121 to prevent any lateral movement of the heat sink relative to the electrical component.

FIG. 3f illustrates a perspective view of semiconductor package 138 with heat sink 122 mounted to back surface 108 of semiconductor die 104 with extensions 124 extending at least partially down side surface 132, or at least partially below surface 108, of the semiconductor die. Semiconductor package 138 is intended to mount to a PCB, see FIG. 6. Extensions 124 stabilize heat sink 122 on electrical component 121 to prevent rotation or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components or create defects on the PCB.

In another embodiment, continuing from FIG. 3a, heat sink or heat spreader 140 is positioned over TIM 120 and back surface 108 of electrical component 121, as shown in FIG. 4a. Heat sink 140 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Heat sink 140 includes angled sides 144 bent or angled downward on two sides from surface 146 of the heat sink. Angled sides 144 can be made by bending the edges of heat sink 140 in a bender machine. Angles sides 144 may have an angle θ of 90-135 degrees with respect to surface 146. The bottom view of heat sink 140 in FIG. 4b shows bent or angled sides 144 continuing along two sides the heat sink to form internal area 150. Angled sides 144 are bent to extend downward to contact or otherwise reside outside of side surface 132 of electrical component 121. FIG. 4c is a perspective view of surface 146 of heat sink 140 with angled sides 144. FIG. 4d illustrates heat sink 140 mounted to back surface 108 of semiconductor die 104, with two sides 144 of heat sink 140 bent down.

In particular, to maintain alignment of heat sink 140, angled sides 144 extend at least partially down side surface 132 of electrical component 121 to hold the electrical component within internal area 150. In another perspective, angled sides 144 extend at least partially below surface 108 of electrical component 121. Angled sides 144 extending at least partially down side surface 132, or at least partially below surface 108, holds heat sink 140 in place relative to semiconductor die 104 to prevent the heat sink from rotating or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components. Heat sink 140 will be fixed in position relative to electrical component 121 by nature of angled sides 144 to prevent any lateral movement of the heat sink relative to the electrical component.

FIG. 4e illustrates a perspective view of semiconductor package 158 with heat sink 140 mounted to back surface 108 of semiconductor die 104 with angled surfaces 144 extending at least partially down side surface 132, or at least partially below surface 108, of the semiconductor die. Semiconductor package 158 is intended to mount to a PCB, see FIG. 6. Angled sides 144 stabilize heat sink 140 on electrical component 121 to prevent rotation or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components or create defects on the PCB.

In another embodiment, continuing from FIG. 3a, heat sink or heat spreader 160 is positioned over TIM 120 and back surface 108 of electrical component 121, as shown in FIG. 5a. Heat sink 160 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Heat sink 160 includes indentations 164 extending at least partially down from surface 166 of the heat sink. Indentations 164 can be made by driving into surface 168 of heat sink 160 with a punch to form the indentation. In another perspective, indentations 164 extend at least partially below surface 108 of electrical component 121. Indentations 164 are punched to extend downward from surface 166 to contact or otherwise reside outside of side surface 132 of electrical component 121. The bottom view of heat sink 160 in FIG. 5b shows indentations 164 continuing along at least two sides semiconductor die 104 to form internal area 170. In one embodiment, indentations 164 have a height H1 of 50-100 μm above surface 166, as shown in FIG. 5c. Indentations 164 may exist on three sides or four sides of heat sink 160. FIG. 5d is a perspective view of surface 166 of heat sink 160 with indentations 164. FIG. 5e illustrates heat sink 160 mounted to back surface 108 of semiconductor die 104.

In particular to maintain alignment of heat sink 160, back surface 108 of electrical component 121 is completely encompassed within internal area 170 so that indentations 164 extend at least partially down side surface 132 of the semiconductor die or at least partially below surface 108. Indentations 164 extending at least partially down side surface 132, or at least partially below surface 108, hold heat sink 160 in place relative to semiconductor die 104 to prevent the heat sink from rotating or otherwise shifting position to impart movement in the lateral direction and contacting adjacent components. Heat sink 160 will be fixed in position relative to electrical component 121 by nature of indentations 164 to prevent any lateral movement of the heat sink relative to the electrical component.

FIG. 5f illustrates a perspective view of semiconductor package 178 with heat sink 160 mounted to back surface 108 of semiconductor die 104 with indentations 164 extending at least partially down side surface 132, or at least partially below surface 108, of the semiconductor die. Semiconductor package 178 is intended to mount to a PCB, see FIG. 6. Indentations 164 stabilize heat sink 160 on electrical component 121 to prevent rotation or otherwise shifting position that would impart movement in the lateral direction and possibly contact adjacent components or create defects on the PCB.

FIG. 6 illustrates electronic device 300 having a chip carrier substrate or PCB 302 with a plurality of semiconductor packages mounted on a surface of PCB 302, including semiconductor packages 138, 158, and 178. Electronic device 300 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

Electronic device 300 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 300 can be a subcomponent of a larger system. For example, electronic device 300 can be part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, ASIC, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

In FIG. 6, PCB 302 provides a general substrate for structural support and electrical interconnect of the semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed over a surface or within layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces 304 provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 304 also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to the PCB. For the purpose of illustration, several types of first level packaging, including bond wire package 306 and flipchip 308, are shown on PCB 302. Additionally, several types of second level packaging, including ball grid array (BGA) 310, bump chip carrier (BCC) 312, land grid array (LGA) 316, multi-chip module (MCM) or SIP module 318, quad flat non-leaded package (QFN) 320, quad flat package 322, embedded wafer level ball grid array (eWLB) 324, and wafer level chip scale package (WLCSP) 326 are shown mounted on PCB 302. In one embodiment, eWLB 324 is a fan-out wafer level package (Fo-WLP) and WLCSP 326 is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

1. A method of making a semiconductor device, comprising: providing an electrical component; anddisposing a heat sink over the electrical component, wherein a portion of the heat sink extends at least partially down a side surface of the electrical component to prevent lateral movement of the heat sink with respect to the semiconductor die.

2. The method of claim 1, wherein the heat sink includes an angled side.

3. The method of claim 1, wherein the heat sink includes an extension.

4. The method of claim 1, wherein the heat sink includes an indentation.

5. The method of claim 1, further including disposing a thermal interface layer between the electrical component and heat sink.

6. The method of claim 1, wherein the portion of the heat sink extends at least partially down at least two side surfaces of the electrical component.

7. A method of making a semiconductor device, comprising: providing an electrical component; anddisposing a heat sink over the electrical component, wherein a portion of the heat sink extends at least partially below a surface of the electrical component.

8. The method of claim 7, wherein the heat sink includes an angled side.

9. The method of claim 7, wherein the heat sink includes an extension.

10. The method of claim 7, wherein the heat sink includes an indentation.

11. The method of claim 7, further including disposing a thermal interface layer between the electrical component and heat sink.

12. The method of claim 7, wherein the portion of the heat sink extends at least partially down at least two side surfaces of the electrical component.

13. The method of claim 7, wherein the electrical component includes a flipchip semiconductor die.

14. A semiconductor device, comprising: an electrical component; anda heat sink disposed over the electrical component, wherein a portion of the heat sink extends at least partially down a side surface of the electrical component to prevent lateral movement of the heat sink with respect to the semiconductor die.

15. The semiconductor device of claim 14, wherein the heat sink includes an angled side.

16. The semiconductor device of claim 14, wherein the heat sink includes an extension.

17. The semiconductor device of claim 14, wherein the heat sink includes an indentation.

18. The semiconductor device of claim 14, wherein the portion of the heat sink extends at least partially down at least two side surfaces of the electrical component.

19. The semiconductor device of claim 14, wherein the electrical component includes a flipchip semiconductor die.

20. A semiconductor device, comprising: an electrical component; anda heat sink disposed over the electrical component, wherein a portion of the heat sink extends at least partially below a surface of the electrical component.

21. The semiconductor device of claim 20, wherein the heat sink includes an angled side.

22. The semiconductor device of claim 20, wherein the heat sink includes an extension.

23. The semiconductor device of claim 20, wherein the heat sink includes an indentation.

24. The semiconductor device of claim 20, wherein the portion of the heat sink extends at least partially down at least two side surfaces of the electrical component.

25. The semiconductor device of claim 20, wherein the electrical component includes a flipchip semiconductor die.