This application claims priority to Japanese Patent Application No. 2003-381282 filed Nov. 11, 2003 which is hereby expressly incorporated by reference herein in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device such as a phase locked loop (PLL) circuit sensitive to interference between signals, i.e., a crosstalk.
2. Related Art
There are cases where the digital signal metal wiring 202 and the analog signal metal wiring 203 need to cross due to the arrangement of the above described plurality of circuit blocks, and in order to carry out the crossing, for example, the analog signal metal wiring 203 has a three-dimensional structure, as shown in
However, because there is the possibility that crosstalk from the digital signal metal wiring 202 in the lower layer 210 to the analog signal wiring portion 203b in the upper layer 220 may arise, a shield wiring 205 needs to be arranged in the lower layer 210 in order to shield between the digital signal metal wiring 202 and the analog signal wiring portion 203b, and thereby, the silicon substrate 201 needs to be extended in the horizontal direction. This causes a problem in that the area of the silicon substrate 201 needs to be enlarged.
A first semiconductor device according to the present invention has a plurality of circuits constituted by a multilayer structure on a substrate, wherein the plurality of circuits are arranged so that one wiring of a plurality of wirings between the plurality of circuits in one layer of the multilayer structure and another wiring of the plurality of wirings in another layer of the multilayer structure do not cross each other.
Moreover, a second semiconductor device according to the present invention has a plurality of circuits constituted by a multilayer structure on a substrate, wherein the plurality of circuits are arranged so that one wiring and another wiring of a plurality of wirings between the plurality of circuits extend in the same layer of the multilayer structure.
According to the first and the second semiconductor devices of the present invention, because the plurality of circuits are arranged so that the one wiring in the one layer of the multilayer structure and the other wiring of the other layer of the multilayer structure do not cross each other, and moreover, because the plurality of circuits are arranged so that the one wiring and the other wiring extend in the same layer of the multilayer structure, a shield wiring between the one wiring and the other wiring, which would be needed if both wirings crossed, is not required. This enables the reduction of the area of the substrate as compared with the conventional art.
A first PLL circuit according to the present invention has a phase comparator, a charge pump, a filter, a voltage controlled oscillator, and a frequency divider constituted by a multilayer structure on a substrate, wherein the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are arranged so that one wiring of a plurality of wirings between the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider in one layer of the multilayer structure, and another wiring of the plurality of wirings in another layer of the multilayer structure do not cross each other.
A second PLL circuit according to the present invention is the PLL circuit having a phase comparator, a charge pump, a filter, a voltage controlled oscillator, and a frequency divider constituted by a multilayer structure on a substrate, wherein the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are arranged so that one wiring and another wiring of a plurality of wirings between the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider extend in the same layer of the multilayer structure.
According to the first and the second PLL circuits of the present invention, because the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are arranged so that the one wiring and the other wiring do not cross each other or the one wiring and the other wiring extend in the same layer of the multilayer structure, a shield wiring between the one wiring and the other wiring, which would be needed if both wirings crossed, is not needed. This enables the reduction of the area of the substrate as compared with the conventional art.
In the PLL circuit according to the above described present invention, it is desirable that the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are arranged so that the plurality of wirings, an input signal wiring to the phase comparator circuit, and an output signal wiring from the voltage controlled oscillator do not cross each other.
In the PLL circuit according to the above described present invention, it is desirable that the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider are arranged so that the plurality of wirings, an input signal wiring to the phase comparator circuit, and an output signal wiring from the voltage controlled oscillator extend in the same layer of the multilayer structure.
In the PLL circuit according to the above described present invention, it is desirable that a first distance between the charge pump and the voltage controlled oscillator is longer than a second distance between two mutually adjoining members of the group including the phase comparator, the charge pump, the voltage controlled oscillator, and the frequency divider.
In the PLL circuit according to the above described present invention, it is desirable that a transistor which functions as a capacitor in the filter is provided between the charge pump and the voltage controlled oscillator.
In the PLL circuit according to the above described present invention, it is desirable that a plurality of transistors which function as a capacitor in the filter are provided in the periphery of the voltage controlled oscillator.
In the PLL circuit according to the above described present invention, it is desirable that a bypass capacitor between a power supply wiring for supplying electric power to one of the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency dividers, and ground is provided near the filter.
In the PLL circuit according to the above described invention, it is desirable that the bypass capacitor is provided on the outside of a closed region virtually formed by joining the phase comparator, the charge pump, the filter, the voltage controlled oscillator, and the frequency divider.
Embodiments of the semiconductor device according to the present invention will be described with reference to accompanying drawings. PLL circuits of a first embodiment through a third embodiment are semiconductor devices mounted in, for example, a cellular phone ASIC, an LCD panel ASIC, a low power microcomputer IC and an LSI for clocks, or the like, and are constituted by a multilayer structure on a semiconductor substrate.
The input portion 10 receives, for example, from an external quarts crystal oscillator (not shown), an input signal S1 whose frequency is stabilized and which is generated by vibration of the crystal oscillator, and the input signal S1 is inputted to the phase comparator 20.
The phase comparator 20 detects the phase difference between the input signal S1 inputted to the input portion 10, and a signal S7 outputted from the frequency divider 60, and outputs a signal S3 (hereinafter, referred to as “phase difference signal S3”), which indicates the phase difference, to the charge pump 30.
The charge pump 30 generates an electric current corresponding to the phase difference signal S3 which is outputted from the phase comparator 20, and outputs an electric current S4 to the filter 40.
The filter 40 is composed of a low pass filter, i.e., an integrating circuit, and smoothly outputs a voltage S5 corresponding to the amount of the electric current S4 supplied from the charge pump 30, to the voltage controlled oscillator 50.
The voltage controlled oscillator 50 is composed of a so-called VCO (Voltage Controlled Oscillator), generates an oscillation signal S6 having a frequency provided by a voltage S5 that is outputted from the filter 40, and outputs the oscillation signal S6 to the frequency divider 60, while outputting an oscillation signal S2, which is the same as the oscillation signal S6, to the output portion 70.
The frequency divider 60 outputs a frequency division signal S7 obtained by dividing-by-N (N is an arbitrary positive number) the oscillation signal S6 outputted from the voltage controlled oscillator 50, to the phase comparator 20.
The output portion 70 outputs the oscillation signal S2 outputted from the voltage controlled oscillator 50 to an external circuit, for example, to a frequency conversion circuit (not shown) for a cellular phone ASIC, an LCD panel ASIC, and/or a low power microcomputer for a clock.
In addition, a bypass capacitor 100 to be coupled between a power supply wiring 90 for supplying electric power to the input portion 10 through the output portion 70, and a ground potential, which has a conventionally known function, is arranged adjacent to the filter 40. More precisely, the bypass capacitor 100 is arranged on the outside of the filter 40, i.e., on the outside of a closed region virtually formed by joining the phase comparator 20 through the frequency divider 60 in this order.
As described above, in the PLL circuit 1 of embodiment 1, the phase comparator 20 through the frequency divider 60 are arranged so that the wirings for the signals S3 through S7, which are the wirings between the functional blocks 20 through 60, do not cross each other, i.e., extend in the same layer, it is not necessary to provide a shield wiring, which would be needed if the wirings for the signals S3 through S7 crossed each other, for avoiding interference between the signals. Therefore, unlike conventionally, the width of the silicon substrate 2 illustrated in
In addition, because the input portion 10 and the output portion 70 are arranged so that the wiring for the signal S1 and the wiring for the signal S2, which are not the wiring between the functional blocks, do not cross each other, i.e., extend in the same layer, it is not necessary to provide a shield wiring, which would be needed if both wirings for the signals S1 and S2 crossed, and as a result, the area of the silicon substrate 2 illustrated in
Moreover, because the wirings for the signals S1 through S7 do not cross, the wirings for the signals S1 through S7 are short as compared with the conventional art, and thereby the wiring resistance can be reduced, and as a result, the crosstalk between the signals can be reduced and the electric current consumed can be also reduced.
Furthermore, because the bypass capacitor 100 is provided near the filter 40, modifications to the function of the filter 40 and the function of the bypass capacitor 100 can be easily made by changing the wiring connection between the bypass capacitor 100 and the capacitor in the filter 40.
The above described modifications to the function can be easily made by arranging the above described bypass capacitor 100 inside the closed region, instead of arranging it outside of the closed region that is virtually formed by joining the phase comparator 20 through the frequency divider 60.
The PLL circuit of embodiment 2 has the input portion 10 through the output portion 70, which are functional blocks like the PLL circuit of embodiment 1, and the functional blocks are mutually coupled by wirings for the signals S1 through S7.
The transistor 120 is a conventionally known FET (Field Effect Transistor). One end of the resistor 110 is coupled to the wirings for the signals S4 and S5, another end of the resistor 110 is coupled to a gate electrode 120a of the transistor 120, and a drain electrode 120b and a source electrode 120c of the transistor 120 are coupled to a ground potential. The transistor 120 itself functions as a capacitor by the connection of the transistor 120, and functions as a low pass filter cooperating with the resistor 110.
As described above, in the PLL circuit 1 of embodiment 2, because the input portion 10 through the output portion 70 are arranged like embodiment 1 so that the wirings for the signals S1 through S7 do not cross each other, and in addition, because the distance between the charge pump 30 and the voltage controlled oscillator 50 is long as compared with the distances between other functional blocks as described above, the occurrence of signal interference between the charge pump 30, which is sensitive to signal interference, and the voltage controlled oscillator 50, can be suppressed.
Moreover, in the PLL circuit 1 of embodiment 2, because the transistor 120 which functions as a capacitor for the filter 40 is arranged between the charge pump 30 and the voltage controlled oscillator 50, the free space of the charge pump 30 and the voltage controlled oscillator 50 can be utilized effectively.
The PLL circuit of embodiment 3 has the input portion 10 through the output portion 70 like the PLL circuit of embodiment 1 and embodiment 2, and the input portion 10 through the output portion 70 are mutually coupled by the wirings for the signals S1 through S7 like embodiment 1 and embodiment 2.
The transistors 130, 140, and 150 actually function in the same manner as the capacitor which is the function of the transistor 120 of embodiment 2 by mutually cooperating and functioning, and thereby, the resistor 110 and the transistors 130, 140, and 150 play a role as a low pass filter, as the entire filter 40.
In addition, the transistor 130 illustrated in
As described above, in the PLL circuit 1 of embodiment 3, like embodiment 1 and embodiment 2, the input portion 10 through the output portion 70 are arranged so that the wirings for the signals S1 through S7 do not cross each other, and in addition, because the transistors 130, 140, and 150 which constitute the filter 40 are arranged near the voltage controlled oscillator 50, the voltage controlled oscillator 50, which easily gives and receives signal interference, can be effectively isolated from the other functional blocks, and thereby, signal interference between the voltage controlled oscillator 50 and the other functional blocks can be reduced as compared with the conventional art.
Although the description above has been made with reference to preferred embodiments, it should be understood that various modifications may be made to the embodiments without departing from the spirit and scope of the present invention.
Number | Date | Country | Kind |
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2003-381282 | Nov 2003 | JP | national |