Patent Application
20170040824
The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) type semiconductor device and a semiconductor module that are used as a cell balance circuit of a charging circuit configured to charge a plurality of batteries.
When a plurality of secondary batteries are connected in series in a charge and discharge circuit of a secondary battery such as a lithium ion battery, the individual secondary batteries have variation in their battery voltages in some cases. Such variation in the battery voltages of the secondary batteries leads to overdischarge and overcharge in some secondary batteries, resulting in degradation of the secondary batteries.
In order to reduce such variation in the battery voltages of secondary batteries, NPL 1 discloses a circuit in which a MOSFET and a resistor are connected in parallel with the individual secondary battery. In this circuit, when the battery voltage of the individual secondary battery becomes equal to or larger than a predetermined voltage, the MOSFET connected with the secondary battery is controlled to be turned on. When the MOSFET is turned on, the secondary battery connected with the MOSFET is discharged through the resistor, and the battery voltage decreases accordingly. This allows adjustment of a balance between the battery voltages of a plurality of the secondary batteries, and to prevent overcharge and overdischarge of the secondary batteries, and hence degradation thereof. The resistor sets a discharge current value of each secondary battery through its resistance.
When the MOSFET is turned on, the resistor connected with the MOSFET generates heat. Thus, with a configuration in which the resistor and the MOSFET are disposed close to each other, the heat generated by the resistor potentially causes malfunction of the MOSFET. In order to prevent this malfunction, in the circuit disclosed in NPL 1, the resistor and the MOSFET are separately mounted as individual components on a printed wiring board.
When a battery, or a battery cell (hereinafter simply referred to as a battery) included in the battery is charged, the batteries are connected in series, and then voltage is applied to the batteries connected in series to boost each battery to a predetermined voltage. When the batteries connected in series are charged, and the charging is continued without being stopped each time one battery reaches a predetermined voltage while each cell being charged has a voltage different from voltages of other cells, the battery becomes overcharged. In order to charge all batteries to a predetermined voltage, provided is a cell balance circuit configured to stop charging and discharge a cell each time any one of the batteries reaches the predetermined voltage. The cell balance circuit stops charging each time one battery reaches a predetermined voltage while a plurality of batteries are charged, and discharges only this battery under control of the cell balance circuit until a constant voltage is reached. Thereafter, the cell balance circuit again performs charging, and repeats charging and discharging until all batteries reach the predetermined voltage. In this manner, the cell balance circuit performs charging of all batteries until the batteries reach the predetermined voltage without overcharge of any battery.
The following describes the cell balance circuit and a charging circuit including the cell balance circuit with reference to
As illustrated in
Cell balance circuit 143 with such a configuration stops charging each time one battery 121 is charged up to a predetermined voltage, and turns on MOSFET 122 connected with battery 121 under control of the control circuit to discharge battery 121 to a constant voltage. After discharging to the constant voltage, cell balance circuit 143 turns off MOSFET 122 to stop discharging and starts charging of batteries 121 connected in series. This operation is repeated until all of batteries 121 are charged to the predetermined voltage. In this manner, all of batteries 121 are charged to the predetermined voltage while being prevented from overcharge.
NPL1: Toranjisuta gijutsu(Transistor Technology) (January 2014), CQ Publishing Co., Ltd., Jan. 1, 2014, pp. 62 to 64
However, in a protection circuit disclosed in NPL 1, one resistor is needed for one MOSFET, and thus the number of components mounted on a printed wiring board increases, leading to a larger mounting area occupying the printed wiring board. In recent years, reduction has been required in the size and weight of a semiconductor component, and thus it is important to solve the above problem. In particular, in a component mounted on an automobile requiring a higher reliability than other commercial products, an increased number of connections between components by, for example, soldering leads to an increased number of soldering failure at the connections, which is degradation of reliability. Although the components are required to be incorporated in a semiconductor device, when a resistor in the above-described protection circuit is incorporated into a semiconductor device with high integration of elements, a shorter distance between a MOSFET and the resistor as a heat source adversely causes malfunction of the MOSFET due to heat generated in the resistor.
In addition, recently, a shorter time has been required for charging of a battery, and for example, a time taken for discharging in cell balance circuit 143 in
However, the reduction in the resistance of discharge resistor 123 leads to an increase in a generated heat amount. In other words, the generated heat amount is proportional to an electric power consumption P, which is determined by Expression (1) below.
P=IV=I(IR)=I2R (1)
In the expression, I represents a current value [A] of the discharge current, and R represents a resistance [Ω] of the discharge resistor.
According to Expression (1), a larger discharge current leads to a larger generated heat amount. Then, a larger generated heat amount thermally affects battery 121 and its surrounding circuits, and in particular, causing fire on battery 121, which is a problem in safety. For this reason, a rise in temperature needs to be reduced, but the reduction of the temperature rise requires reduction in the discharge current by increasing the resistance of discharge resistor 123. The reduction in the discharge current to achieve a larger resistance of discharge resistor 123, however, adversely results in degradation of discharging efficiency. Thus, in cell balance circuit 143, the discharging efficiency and the generated heat amount have a trade-off relation therebetween.
The present invention intends to solve the above-described problem, and it is an object of the present invention to prevent malfunction of a MOSFET by reducing a number of components mounted on a printed wiring board to achieve a smaller mounting area of the components, to achieve improved discharging efficiency by reducing a resistance of a discharge resistor at low temperature, and to reduce a generated heat amount by increasing the resistance at higher temperature.
A semiconductor device in which a discharge switch MOSFET of a cell balance circuit used for a charging circuit configured to charge a plurality of batteries is integrated on a semiconductor substrate further includes a discharge resistor integrated on the semiconductor substrate, and a resistance electrode integrated on the discharge resistor. The discharge resistor includes a first terminal surface connected with a drain terminal of the MOSFET, a second terminal surface connected with the resistance electrode, and an insulation surface insulating between the first terminal surface and the second terminal surface. The first terminal surface is electrically connected with the drain terminal of the MOSFET. The second terminal surface is in contact with and electrically connected with the resistance electrode in an entire region of an upper surface of the discharge resistor except for the first terminal surface and the insulation surface. When the semiconductor device is mounted on a component mounting surface of a mount substrate on which the cell balance circuit is mounted, with an upper surface of the semiconductor device facing to the component mounting surface, the resistance electrode is jointed to a terminal joint on the component mounting surface of the mount substrate through a joint material allowing electric conduction, and when one of the plurality of batteries is discharged, both terminals of the battery are electrically connected with the resistance electrode and a source terminal of the MOSFET, respectively, and conduction between the drain terminal and the source terminal of the MOSFET is controlled.
A semiconductor device in which a discharge switch MOSFET of a cell balance circuit used for a charging circuit configured to charge a plurality of batteries is integrated on a semiconductor substrate further includes a discharge resistor integrated the semiconductor substrate. One of terminals of the discharge resistor is connected with a drain terminal of the MOSFET. A resistance of the discharge resistor has a positive temperature dependency. When one of the plurality of batteries is discharged, both terminals of the battery are electrically connected with the other terminal of the discharge resistor and a source terminal of the MOSFET, respectively, and conduction between a drain terminal and the source terminal of the MOSFET is controlled.
According to a MOSFET semiconductor device of the present invention, the MOSFET and a resistance film serving as a resistor are formed in one semiconductor device, thereby achieving reduction in a number of components as compared to a case in which these are separately mounted as individual components on a printed wiring board, and hence achieving reduction in a mounting area of the components.
A resistance electrode of the semiconductor device is a surface mount terminal, and the semiconductor device is flip-mounted on the printed wiring board by using a joint material, a terminal surface connected with a resistance electrode of a discharge resistor is in contact with the resistance electrode in an entire region of the terminal surface except for a terminal surface connected with a drain terminal, and an insulation surface, so as to provide a larger contact area for more efficient thermal conduction of heat generated in the resistance film. Accordingly, the heat generated in the resistance film is radiated to the printed wiring board through the resistance electrode. The resistance electrode, the joint material, and the printed wiring board are made of a metal having a high thermal conductivity to further increase heat radiation efficiency. This can prevent malfunction of the MOSFET due to the heat.
Moreover, incorporation of a resistor and a diode in a semiconductor module into the semiconductor device can achieve a reduced number of connections between components in the semiconductor module by, for example, soldering. In particular, a reduced failure rate can be achieved for a component mounted on an automobile requiring a higher reliability than other commercial products.
In addition, the MOSFET and the discharge resistor are integrated on one chip, and the discharge resistor is provided with a positive temperature dependency, so that a larger resistance of the discharge resistor can be achieved at a higher temperature, and reduction in a generated heat amount can also be achieved in the discharge resistor, so as to prevent a high temperature of the circuit. The discharge resistor has a smaller resistance at low temperature, which leads to an increased discharge current, so that this achieves improved discharging efficiency.
The following describes, with reference to
A land grid array (LGA) chip size package may be used in place of the BGA chip size package.
Similarly to
Circumference of resistance film 373 is covered by insulating film 374. A partial region including a region at a central part of resistance film 373 is exposed from insulating film 374, and in contact with surface mount terminal 350. Surface mount terminal 350 includes, on a side closer to the semiconductor device, aluminum layer 375 formed by aluminum sputtering on a resistance film, and nickel layer 376 formed as a lowermost layer by plating.
Semiconductor device 300 is mounted on printed wiring board 360 by jointing nickel layer 376 and copper wiring 352 of a connection terminal on printed wiring board 360 by soldering.
With the above-described configuration, a discharge resistor used for the cell balance circuit is integrated as a resistance film with the semiconductor device. Accordingly, a number of components of the cell balance circuit mounted on the printed wiring board, and thus a mounting area of the components can be reduced, and heat generated in resistance film 373 is radiated through surface mount terminal 350, solder 351, and printed wiring board 360. With this configuration, for example, a distance between the discharge resistor and the printed wiring board can be reduced and an area of a heat radiation path can be increased as compared to a configuration in which nickel layer 376 and copper wiring 352 connected through a wire. When material such as metal having a high thermal conductivity is used for an electrode and a joint material on the heat radiation path, heat generated in the discharge resistor can be efficiently transferred through the printed wiring board. This can prevent malfunction of the MOSFET due to heat.
Examples of a material of solder 351 include, but are is not limited to, Sn—Pb based material, Pb—Sn—Sb based material, Sn—Sb based material, Sn—Pb—Bi based material, Bi—Sn based material, Sn—Cu based material, Sn—Pb—Cu based material, Sn—In based material, Sn—Ag based material, Sn—Pb—Ag based material, and Pb—Ag based material. A material of copper wiring 352 is not limited to copper, iron, nickel, gold, aluminum, and alloys thereof.
The following describes the MOSFET semiconductor device according to the present first exemplary embodiment with reference to
First principal surface 10a refers to a surface of semiconductor substrate 10 facing to the printed wiring board when MOSFET semiconductor device 1 according to the present first exemplary embodiment is mounted on the printed wiring board (mount substrate), and second principal surface 10b refers to another surface of semiconductor substrate 10 opposite to first principal surface 10a. Source electrode S, gate electrode G, drain electrode D, and insulating film 21 are formed on first principal surface 10a of semiconductor substrate 10. Resistance film 22 serving as a resistor is formed on insulating film 21, and resistance electrode R is formed on resistance film 22. Although
Specifically, source electrode S, gate electrode G, drain electrode D, and resistance electrode R are formed on a side closer to first principal surface 10a, and thus are terminals to be jointed when the semiconductor device is flip-mounted on the printed wiring board at surface mounting. Thus, MOSFET semiconductor device 1 can be mounted on the printed wiring board by, for example, reflow without using a wire or the like.
Resistance film 22 is directly connected with drain electrode D. As illustrated in
In semiconductor substrate 10, P-type semiconductor layer 11, N-type diffusion layer 12, and P-type diffusion layer 13 are formed in a region below source electrode S in this order in a direction from second principal surface 10b toward first principal surface 10a, and only P-type semiconductor layer 11 is formed in a region below drain electrode D and insulating film 21. Since insulating film 21 is disposed between resistance film 22 and P-type semiconductor layer 11, P-type semiconductor layer 11 and resistance film 22 are electrically insulated.
As illustrated in
Gate insulating film 20 is formed on an inner surface of trench 14, and gate electrode G is formed further inside gate insulating film 20. In other words, gate electrode G faces N-type diffusion layer 12 to interpose gate insulating film 20 therebetween.
Protection film 23 has openings such that source electrode S, gate electrode G, drain electrode D, and resistance electrode R are at least partially exposed from protection film 23 and covers a surface of the MOSFET semiconductor device on the side closer to first principal surface 10a. For example, as illustrated in
Metal film 24 is a metal member having a low resistance and formed on second principal surface 10b of semiconductor substrate 10, and functions to conduct, to drain electrode D at high energy efficiency, current flowing from source electrode S toward second principal surface 10b of semiconductor substrate 10.
For example, when secondary battery B1 has a battery voltage equal to or higher than a predetermined voltage, such a control is performed to turn on the MOSFET of MOSFET semiconductor device 1 connected with secondary battery B1. When the MOSFET is turned on, secondary battery B1 is discharged through resistance film 22 serving as a resistor, and the battery voltage of secondary battery B1 decreases accordingly. When secondary battery B2 has a battery voltage lower than the predetermined voltage, such a control is performed to turn off a MOSFET connected with secondary battery B2. When the MOSFET is turned off, secondary battery B2 is not discharged through resistance film 22 but is charged through a charging circuit not illustrated. In this manner, only one of two secondary batteries B1 and B2 can be charged by controlling turning on and off of the two MOSFETs.
This configuration allows adjustment of balance of battery voltage, and prevention of overcharge and overdischarge of secondary batteries B1 and B2 to further prevent degradation of the secondary batteries. When two secondary batteries or more are connected in series with each other, the individual secondary batteries may be each connected in parallel with MOSFET semiconductor device 1 according to the present first exemplary embodiment depending on this number of the secondary batteries. When the MOSFET connected with secondary battery B1 is turned on, current I flows from a positive terminal of secondary battery B1 to a negative terminal of secondary battery B1 through the MOSFET and resistance film 22. Current I has a current value determined by a resistance of resistance film 22.
In MOSFET semiconductor device 1 according to the present first exemplary embodiment, the MOSFET including semiconductor substrate 10, source electrode S, gate electrode G, drain electrode D, and gate insulating film 20, and resistance film 22 serving as a resistor are formed in one semiconductor device. With this configuration, the number of components and hence the mounting area of the components can be reduced as compared to a case in which these are separately mounted as individual components on the printed wiring board.
The following describes an operation of the MOSFET semiconductor device according to the present first exemplary embodiment with reference to
As described above, drain electrode D is electrically connected with resistance electrode R through resistance film 22. Thus, current I in drain electrode D flows to resistance electrode R through resistance film 22. Then, since resistance electrode R is a surface mount terminal, heat generated by current I passing through resistance film 22 is radiated toward the printed wiring board through resistance electrode R. Accordingly, this prevents malfunction of the MOSFET when being heated.
As illustrated in
According to an aspect of the semiconductor device of the present invention, the insulating film separating drain electrode D and resistance electrode R from each other may cover not only the upper surface of resistance film 22 but also part of a side surface of resistance film 22.
In addition, resistance film 22 preferably has a circular shape because the current between drain electrode D and resistance electrode R flows in uniformly in all directions, and thus the heat can be more efficiently dispersed. The circular shape is a circular disk shape when resistance film 22 has no opening as illustrated in
According to an aspect of the semiconductor device of the present invention, the shape of the resistance film in plan view is not limited to a circular shape including an ellipse but may be a polygonal shape.
The following describes a method of manufacturing the MOSFET semiconductor device according to the first exemplary embodiment of the present invention with reference to
Then, as illustrated in
Next, as illustrated in
Thereafter, as illustrated in
Then, as illustrated in
Next, as illustrated in
Then, as illustrated in
Thereafter, as illustrated in
Finally, as illustrated in
With this configuration, resistance film 22 serving as a resistor is formed in a process of manufacturing the semiconductor device, which eliminates a need to separately prepare a resistor, and achieves a reduced cost as compared to the conventional manufacturing method. In addition, since resistance film 22 is formed in the process of manufacturing the semiconductor device, a resistance can be accurately controlled as compared to the conventional resistor.
Since resistance film 22 is formed between drain electrode D and resistance electrode R, which are surface mount terminals, and a resistance between drain electrode D and resistance electrode R is equivalent to the resistance of resistance film 22, the resistance of resistance film 22 can be measured easily.
In the MOSFET semiconductor device and the method of manufacturing the MOSFET semiconductor device according to the present first exemplary embodiment, the MOSFET including semiconductor substrate 10, source electrode S, gate electrode G, drain electrode D, and gate insulating film 20, and resistance film 22 serving as a resistor are formed in one semiconductor device, and thus the number of components and hence the mounting area of the components can be reduced as compared to the case in which these are separately mounted as individual components on the printed wiring board.
Since drain electrode D is electrically connected with resistance electrode R through resistance film 22, current flowing into drain electrode D flows to resistance electrode R through resistance film 22. Then, since resistance electrode R is a surface mount terminal, heat generated by current I passing through resistance film 22 is radiated toward the printed wiring board through resistance electrode R. Accordingly, this prevents malfunction of the MOSFET when being heated.
In the present first exemplary embodiment, P-type semiconductor layer 11, N-type diffusion layer 12, and P-type diffusion layer 13 are formed on semiconductor substrate 10, but all of these channels may be inverted. Specifically, an N-type semiconductor layer, a P-type diffusion layer, and an N-type diffusion layer may be used in place of P-type semiconductor layer 11, N-type diffusion layer 12, and P-type diffusion layer 13, respectively, according to the present first exemplary embodiment.
For example,
In the present first exemplary embodiment, the vertical MOSFET having a trench structure is used, but the present invention is not limited thereto, the MOSFET may have a planar or lateral structure. For example,
In the present first exemplary embodiment, source electrode S, gate electrode G, drain electrode D, and resistance electrode R are each a surface mount terminal, but the present invention is not limited thereto, and at least resistance electrode R needs to be a surface mount terminal.
In the present first exemplary embodiment, single source electrode S, single gate electrode G, single drain electrode D, and single resistance electrode R are formed, but the present invention is not limited thereto. A plurality of source electrodes S, gate electrodes G, drain electrodes D, and resistance electrodes R may be formed depending on a source-drain current value and a resistance of a resistor for stabilizing this current value.
In the cell balance circuit, the semiconductor device of the present invention is configured as an integration of a switching semiconductor element such as a MOSFET and a discharge resistor on one chip. The discharge resistor is made of polysilicon (polycrystalline silicon film), and provided with a positive temperature dependency by adjusting a dose amount of impurity ions of implanted into polysilicon, and this dependency is adjusted. A resistance of typical polysilicon has a negative temperature dependency or slight temperature dependency. The implantation of impurity ion such as boron into polysilicon provides a positive temperature dependency to the resistance of polysilicon, and a gradient of the dependency can be adjusted through an implantation amount. In this manner, the discharge resistor is adjusted to have a low resistance at low temperature, and a high resistance at high temperature. Accordingly, a large discharge current is provided due to the low resistance at low temperature, and achieves improved discharging efficiency, and a generated heat amount can be reduced due to the high resistance at high temperature. Accordingly, this prevents a high temperature of the circuit.
The discharge resistor is provided on a drain side of the semiconductor element, and thus is preferably formed to be adjacent to the drain terminal of the semiconductor element. The discharge resistor is not limited to polysilicon, but may be a diffusion resistor with an adjusted impurity concentration.
The following describes an example in which the semiconductor element is a MOSFET in the semiconductor device of the present invention and the method of manufacturing the semiconductor device with reference to drawings.
First, the semiconductor device and the method of manufacturing the semiconductor device according to a second exemplary embodiment will be described with reference to
As illustrated in
MOSFET unit 103 includes P-type diffusion layer 107 formed as a body on part of surface 105 of N-type semiconductor substrate 104, N-type diffusion layer 108 formed as a source on part of surface 105 of N-type semiconductor substrate 104 in P-type diffusion layer 107, and gate trench 109 penetrating N-type diffusion layer 108 and P-type diffusion layer 107 from surface 105 of semiconductor substrate 104. N-type diffusion layer 108 is conducted with source terminal 110 formed on surface 105 of semiconductor substrate 104. Gate trench 109 is formed on surface 105 of semiconductor substrate 104 and conducted with a gate terminal (not illustrated) formed insulating from source terminal 110. High-concentration N-type diffusion layer 112 is formed on back surface 111 opposite to surface 105 of semiconductor substrate 104.
Drain extending unit 106 is formed in a region of N-type semiconductor substrate 104 adjacent to MOSFET unit 103. In drain extending unit 106, N-type diffusion layer 113 is formed at least part of surface 105 of N-type semiconductor substrate 104. In drain extending unit 106, an electron flowing from source terminal 110 to N-type semiconductor substrate 104 through N-type diffusion layer 108 and P-type diffusion layer 107 in MOSFET unit 103 is moved to surface 105 of semiconductor substrate 104 through high-concentration N-type diffusion layer 112, N-type semiconductor substrate 104, and N-type diffusion layer 113. N-type diffusion layer 113 is conducted with drain terminal 114 formed on surface 105 of semiconductor substrate 104. Source terminal 110, the gate terminal (not illustrated), and drain terminal 114 are insulated from each other by insulating film 115 on surface 105 of N-type semiconductor substrate 104 and extended to insulating film 115.
MOSFET unit 103 and drain extending unit 106 with such a configuration serve as semiconductor element unit 102.
Discharge resistor unit 101 is formed in a region of N-type semiconductor substrate 104 adjacent to semiconductor element unit 102, preferably in a region adjacent to drain extending unit 106. In discharge resistor unit 101, resistance region 116 made of polysilicon is formed in insulating film 115 on surface 105 of N-type semiconductor substrate 104. Both ends of resistance region 116 are connected with resistance terminal 117 and resistance terminal 118 formed on insulating film 115.
The present invention has such a characteristic that impurity ions are implanted into resistance region 116 to provide a positive temperature dependency to a resistance of polysilicon of resistance region 116 as indicated by line 119 illustrating a temperature-resistance relation in
For example, first, P-type diffusion layer 107, N-type diffusion layer 108, gate trench 109, high-concentration N-type diffusion layer 112, and N-type diffusion layer 113 are formed on N-type semiconductor substrate 104, and then part of insulating film 115 is formed on surface 105. Thereafter, resistance region 116 of polysilicon having a thickness ranging from 100 nm to 500 nm inclusive is formed on the part of insulating film 115 of discharge resistor unit 101. Next, boron ions are implanted into resistance region 116 at a dose amount ranging from 5×1016/cm2 to 5×1016/cm2 inclusive. Next, a remaining part of insulating film 115 is formed. Lastly, selective etching is performed on insulating film 115, and then source terminal 110, the gate terminal (not illustrated), drain terminal 114, resistance terminal 117, and resistance terminal 118 are formed. In the formation, drain terminal 114 and resistance terminal 118 are conducted with each other. It is preferable that polysilicon has a thin film thickness as possible, for example, of 300 nm or smaller, and boron ions are implanted at a dose amount of 1×1016/cm2.
As described above, the implantation of boron ions provides a positive temperature dependency to the resistance of polysilicon in resistance region 116, achieving resistance R1 of 25Ω at a surrounding temperature of 25° C., and resistance R2 of 50Ω at surrounding temperature of 75° C. Thus, electric power consumption P at low temperature such as the surrounding temperature of 25° C. is calculated to be P=IV=V2/R1=52/25=1 [W] for battery voltage V of 5 V. Electric power consumption P at high temperature such as the surrounding temperature of 75° C. is calculated to be P=IV=V2/R2=52/50=0.5 [W] for battery voltage V of 5 V. Accordingly, the resistance is low at low temperature, achieving a high electric power consumption and thus high discharging efficiency. In contrast, the resistance is high at high temperature, achieving a low electric power consumption and thus reduced heat generation.
The above-described configuration of the cell balance circuit of the semiconductor device will be described with reference to
As illustrated in
When one battery 121 is charged up to a predetermined voltage such as 5 V, cell balance circuit 143 with such a configuration stops the charging and turns on MOSFET 122 connected with this battery 121 under control of control circuit 124 to discharge this battery 121 to a constant voltage such as 4.5 V. After battery 121 is discharged to 4.5 V, cell balance circuit 143 turns off this MOSFET 122 to stop the discharging and resumes charging of batteries 121 connected in series. This operation repeated until all batteries 121 are charged to 5 V. In this manner, all batteries 121 can be charged to 5 V while being prevented from overcharge.
As illustrated in
As described above, the resistance of discharge resistor 123 can have a positive temperature dependency such that a low resistance at low temperature leads to high electric power consumption and hence high discharging efficiency, and a high resistance at high temperature leads to low electric power consumption and hence low heat generation.
The following describes a semiconductor device according to a third exemplary embodiment and a method of manufacturing the semiconductor device with reference to
Although the discharge resistor is made of polysilicon in the semiconductor device according to the second exemplary embodiment, the discharge resistor is a diffusion resistor of a diffusion layer formed on a semiconductor substrate in the semiconductor device according to the third exemplary embodiment.
As illustrated in
In the semiconductor device with such a configuration, a positive temperature dependency of a resistance of N-type diffusion layer 130 can be adjusted by adjusting an impurity concentration of N-type diffusion layer 130 as a resistance region. The resistance of N-type diffusion layer 130 as the discharge resistor can have a positive temperature dependency such that a low resistance at low temperature leads to high electric power consumption and hence high discharging efficiency, and a high resistance at high temperature leads to low electric power consumption and hence low heat generation.
Similarly to the second exemplary embodiment, semiconductor element unit 102 and discharge resistor unit 127 of semiconductor device 128 according to the third exemplary embodiment correspond to the integration of MOSFET 122 and discharge resistor 123 in
The following describes a semiconductor device according to a fourth exemplary embodiment and a method of manufacturing the semiconductor device with reference to
Although a vertical MOSFET is used as the semiconductor element unit in the second and third exemplary embodiments, a lateral MOSFET is used in place of the vertical MOSFET in the second and third exemplary embodiments in the fourth exemplary embodiment.
As illustrated in
In
As described above, in semiconductor device 131 according to the fourth exemplary embodiment, implantation of impurity ions into polysilicon of resistance region 116 of discharge resistor unit 101 provides the resistance of the discharge resistor with a positive temperature dependency. Thus, this achieves a low resistance at low temperature and a high resistance at high temperature. Accordingly, the low resistance of the discharge resistor at low temperature leads to an increase in the discharge current. Therefore, this improves discharging efficiency. The high resistance at high temperature leads to reduction in the generated heat amount. Therefore, this prevents a high temperature of the circuit. Similarly to the first exemplary embodiment, the integration of the MOSFET and the discharge resistor leads to reduction in the number of components and hence in the mounting area. Accordingly, this facilitates mounting of the cell balance circuit and achieves improved quality guarantee of the components.
Although
Next, an exemplary configuration of the cell balance circuit including the semiconductor device of the present invention will be described as a fifth exemplary embodiment with reference to
In the above-described second to fourth exemplary embodiments, the MOSFET in the semiconductor element unit is an N-channel MOSFET. In a semiconductor device in
A charging circuit illustrated in
In this manner, when MOSFET 140 is a P-channel MOSFET, the enable signal is constantly input to MOSFET 140 even at failure of control circuit 124, to discharge any battery 121. This can avoid at least overcharge of battery 121, and guarantee safety.
In the semiconductor device according to the first exemplary embodiment, similarly to the second to fifth exemplary embodiments, the resistance of the resistance film (discharge resistor) can have a positive temperature dependency. Thus, this achieves a low resistance of the discharge resistor at low temperature and a high resistance at high temperature. Accordingly, the low resistance of the discharge resistor at low temperature leads to an increase in the discharge current, thereby achieving improved discharging efficiency, and the high resistance at high temperature leads to a reduction in the generated heat amount, thereby preventing a high temperature of the circuit.
Next, an exemplary configuration of the cell balance circuit including the semiconductor device of the present invention will be described as a sixth exemplary embodiment and a seventh exemplary embodiment with reference to
The following describes, with reference to
First principal surface 319a refers to a surface of N++ semiconductor substrate 319 facing the printed wiring board when semiconductor device 300 according to the present sixth exemplary embodiment is mounted on the printed wiring board (mount substrate), and second principal surface 319b refers to a surface of N++ semiconductor substrate 319 opposite to first principal surface 319a. Source electrode S, gate electrode G, drain electrode D, and insulating film 310 are formed on first principal surface 319a of the semiconductor substrate. Resistance film 311 serving as drive resistance 226 is formed on insulating film 310, and both terminals of drive resistance 226 are connected with gate electrode G and source electrode S, respectively.
In N++ semiconductor substrate 319, N-type epitaxial layer 302, P-type diffusion layer 303, and N-type diffusion layer 304 are formed in this order in a region below source electrode S in a direction from second principal surface 319b toward first principal surface 319a. Only N-type epitaxial layer 302 is formed in a region below gate electrode G and insulating film 310. Resistance film 311 and N-type epitaxial layer 302 are electrically insulated from each other through insulating film 310.
Trench 306 is formed to extend from first principal surface 319a to N-type epitaxial layer 302 through N-type diffusion layer 304 and P-type diffusion layer 303.
Gate insulating film 320 is formed on an inner surface of trench 306, and a gate is formed further inside gate insulating film 320. In other words, the gate faces P-type diffusion layer 303 to interpose gate insulating film 320 therebetween.
The following describes an operation of the MOSFET semiconductor device according to the present sixth exemplary embodiment with reference to
Next, an exemplary configuration of the MOSFET semiconductor device of the present invention will be described as the seventh exemplary embodiment with reference to
As illustrated in
The following describes, with reference to
Control circuit 224 monitors voltages of batteries 221, 231, and the like, and if the voltage of any one of batteries 221 exceeds a predetermined voltage, stops charging and outputs an enable signal to MOSFET 222 connected with battery 221 having a voltage exceeding the predetermined voltage to discharge only this battery 221. In such a charging circuit, MOSFET 222, discharge resistor 223, control circuit 224, and chip resistance 225 if necessary serve as cell balance circuit 243.
When one battery 221 is charged up to a predetermined voltage such as 5 V, cell balance circuit 243 with such a configuration stops the charging and turns on switch 228 inside control circuit 224. Accordingly, current flows from a positive terminal to a negative terminal of this charged battery 221 through drive diode 237 provided between the gate and the source of MOSFET 232 connected in parallel with battery 231 connected in series with the positive terminal, and drive resistance 226 provided between the gate and the source of MOSFET 222.
Potential of the positive terminal of charged battery 221, which was 5 V approximately, drops by a threshold voltage of drive diode 237 of 0.7 V approximately to become 4.3 V approximately, and a potential difference between the gate and the source of MOSFET 232 become −0.7 V approximately, which is not enough to turn on MOSFET 232, but a potential difference of 4.3 V, which is enough to turn on MOSFET 222, occurs between the gate and the source of MOSFET 222.
As described above, MOSFET 222 connected with battery 221 is turned on under control of control circuit 224 to discharge battery 221 to a constant voltage of, for example, 4.5 V. After battery 221 is discharged to 4.5 V, MOSFET 222 is turned off to stop the discharging, and charging of any battery 221 connected in series is resumed. This operation is repeated until all batteries 221 are charged to 5 V. In this manner, all batteries 221 can be charged to 5 V while being prevented from overcharge.
In the semiconductor device according to the sixth and seventh exemplary embodiments, similarly to the first exemplary embodiment, the resistance electrode of the semiconductor device is a surface mount terminal, and the semiconductor device is flip-mounted on the printed wiring board through a joint material. The terminal surface of the discharge resistor connected with the resistance electrode is in contact with the resistance electrode in an entire region of the terminal surface except for the terminal surface connected with the drain terminal, and the insulation surface, so as to provide a larger contact area for more efficient thermal conduction of the heat generated in the resistance film. Accordingly, the heat generated in the resistance film can be radiated to the printed wiring board through the resistance electrode.
In the semiconductor device according to the sixth and seventh exemplary embodiments, similarly to the second to fifth exemplary embodiments, the resistance of the resistance film (discharge resistor) can have a positive temperature dependency to achieve a low resistance of the discharge resistor at low temperature, and a high resistance at high temperature. Accordingly, the low resistance of the discharge resistor at low temperature leads to an increase in the discharge current to achieve improved discharging efficiency. The high resistance at high temperature leads to a reduction in the generated heat amount tp prevent a high temperature of the circuit.
A MOSFET semiconductor device according to the present invention can be suitably used in a charge and discharge circuit of, for example, a lithium ion battery used in a mobile phone or an electric vehicle.
The present invention is useful for, for example, a semiconductor device used for a cell balance circuit of a charging circuit configured to charge a plurality of batteries, and a method of manufacturing the semiconductor device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-094346 | May 2014 | JP | national |
| 2014-108634 | May 2014 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2015/002221 | Apr 2015 | US |
| Child | 15331248 | US |
