SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

Abstract

A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a plan view showing a schematic structure of an aging device having a single-gate structure according to a first embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram showing the aging device according to the first embodiment;

FIG. 3 is a cross-sectional view taken along a line III-III in FIG. 1;

FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 1;

FIG. 5 is a cross-sectional view taken along a line V-V in FIG. 1;

FIGS. 6A to 6C are schematic views illustrating an operational principle of the aging device according to the first embodiment;

FIGS. 7A to 7C are schematic views illustrating the operational principle of the aging device according to the first embodiment;

FIGS. 8A to 8C are schematic views illustrating the operational principle of the aging device according to the first embodiment;

FIGS. 9A to 9C are schematic views illustrating the operational principle of the aging device according to the first embodiment;

FIG. 10 is a plan view showing a schematic structure of an aging device having a single-gate structure according to a second embodiment;

FIG. 11 is a cross-sectional view taken along a line XI-XI in FIG. 10;

FIG. 12 is a plan view showing another example of the aging device according to the second embodiment;

FIG. 13 is a cross-sectional view showing a structure of a second element regional section of an aging device according to a third embodiment, and corresponds to a cross section taken along a line III-III in FIG. 1;

FIG. 14 is another cross-sectional view showing the second element regional section of the aging device according to the third embodiment, and corresponds to a cross-sectional view taken along a line XIV-XIV in FIG. 15;

FIG. 15 is a plan view showing a schematic structure of the aging device according to the third embodiment;

FIG. 16 is a plan view illustrating a semiconductor device according to a fourth embodiment, in which aging devices are connected in parallel as a countermeasure against a normally-off-type defective bit;

FIGS. 17A and 17B are plan views showing arrangement examples of the aging devices;

FIG. 18 is a plan view showing another arrangement example of the aging devices;

FIG. 19 is a plan view showing an example in which the aging devices connected in parallel are dispersed and arranged;

FIGS. 20A and 20B are plan views of examples in which aging devices are connected in series as a countermeasure against a normally-on-type defective bit in order to illustrate a semiconductor device according to a fifth embodiment;

FIG. 21 is a plan view showing an example in which a plurality of series circuits of the aging devices depicted in FIG. 20A are connected in parallel;

FIGS. 22A and 22B are element structure cross-sectional views showing off-on-off-type aging devices in order to illustrate a semiconductor device according to a sixth embodiment;

FIG. 23 is a plan view showing an example in which a plurality of normally-on- and normally-off-type aging devices are connected;

FIG. 24 is a plan view showing an example in which a plurality of normally-on- and normally-off-type aging devices are connected;

FIG. 25 is a plan view showing an example in which a plurality of normally-on- and normally-off-type aging devices are connected;

FIG. 26 is a plan view showing an example in which a plurality of normally-on- and normally-off-type aging devices are connected;

FIG. 27 is a plan view showing an example in which a plurality of aging devices are connected as a countermeasure against an on-off-on-type defective bit in order to illustrate a semiconductor device according to a seventh embodiment;

FIG. 28 is a plan view showing an example in which normally-on series circuits (row) and normally-off series circuits (row) are connected in parallel;

FIG. 29 is a schematic structural view showing a lifetime control circuit with a trimming circuit according to an eighth embodiment;

FIG. 30 is a view showing an example in which a trimming circuit is mounted in a parallelizing circuit;

FIG. 31 is a view showing an example in which a lifetime control circuit is constituted of normally-on circuits and a trimming circuit in order to illustrate a ninth embodiment;

FIG. 32 is a view showing an example in which EEPROMs are used in place of MOS transistors depicted in FIG. 31;

FIG. 33 is a view showing an example in which breakers are used in place of MOS transistors depicted in FIG. 31;

FIG. 34 is a view showing an example in which positions of the breakers and operational circuits depicted in FIG. 33 are exchanged;

FIG. 35 is a view showing an example in which aging devices depicted in FIG. 33 are arranged on a right-hand side of a trimming circuit;

FIG. 36 is a view as a combination of FIGS. 34 and 35, showing an example in which the aging devices are arranged on both sides of the trimming circuit;

FIG. 37 is a view showing an example in which breakers are inserted into a series connection part of the aging devices;

FIG. 38 is a view in which normally-off aging devices are used, showing a relationship between parallel connection of the plurality of aging devices and a trimming circuit;

FIG. 39 is a view as a modification of FIG. 38, showing an example in which the aging devices are arranged on the right-hand side of the trimming circuit;

FIG. 40 is a view showing an example in which positions of the aging devices, the breakers and the operational circuits connected in series are changed in each row;

FIG. 41 is a view showing an example in which FIGS. 33 and 39 are combined; and

FIG. 42 is a schematic structural view showing a lifetime control circuit with a trimming circuit according to a tenth embodiment.

Claims

1. A semiconductor device comprising: a semiconductor substrate;a first semiconductor region and a second semiconductor region formed on the semiconductor substrate to be insulated and separated from each other;a gate dielectric film formed on the semiconductor substrate to overlap the first semiconductor region and the second semiconductor region;a floating gate electrode which is formed on the gate dielectric film and in which a coupling capacitance with respect to the first semiconductor region is larger than a coupling capacitance with respect to the second semiconductor region;first source and drain layers formed on a surface of the first semiconductor region to interpose the floating gate electrode therebetween;a first wiring line connected to one of the first source and drain layers;a second wiring line connected to the other of the first source and drain layers;second source and drain layers formed on a surface of the second semiconductor region to interpose the floating gate electrode therebetween; anda third wiring line connected to the second source and drain layers in common.

2. The semiconductor device according to claim 1, wherein the first wiring line is a bit line, the second wiring line is a source line, and the third wiring line is a word line.

3. The semiconductor device according to claim 2, wherein the bit line and the source line are arranged above the word line and arranged in a direction perpendicular to the word line.

4. The semiconductor device according to claim 1, wherein the gate dielectric film has a thickness which is not smaller than 3.3 nm, and the semiconductor device functions as an electrically rewritable non-volatile semiconductor memory.

5. The semiconductor device according to claim 1, wherein the gate dielectric film has a thickness which is not greater than 3.3 nm, and the semiconductor device functions as an aging device which is turned on or off for a fixed time by storage of electric charge.

6. A semiconductor system constituted by connecting the plurality of semiconductor devices according to claim 5 in parallel or in series.

7. A semiconductor system constituted by connecting in series a series circuit in which the plurality of semiconductor devices according to claim 5 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and a parallel circuit in which the plurality of the semiconductor devices according to claim 5 which are configured to be turned on for a fixed time by storage of electric charge are connected in parallel.

8. The semiconductor system according to claim 7, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is shorter than a time required for all the semiconductor devices included in the parallel circuit to be turned off.

9. A semiconductor system constituted by connecting in parallel a series circuit in which the plurality of semiconductor devices according to claim 5 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and the semiconductor device according to claim 5 which is configured to be turned on for a fixed time by storage of electric charge.

10. The semiconductor system according to claim 9, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is longer than a time required for the semiconductor device configured to be turned on for a fixed time by storage of electric charge to be turned on.

11. The semiconductor device according to claim 1, wherein the floating gate electrode and each of the first semiconductor region and the second semiconductor region have overlapping, and an overlapping area of the floating gate electrode and the first semiconductor region is larger than an overlapping area of the floating gate electrode and the second semiconductor region.

12. The semiconductor device according to claim 1, wherein the floating gate electrode has a T-shape, and a gate width of the floating gate electrode on the first semiconductor region side is larger than a gate width of the floating gate electrode on the second semiconductor region side.

13. The semiconductor device according to claim 1, wherein a dielectric constant of the gate dielectric film on the first semiconductor region side is higher than that of the gate dielectric film on the second semiconductor region side.

14. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region have a p type conductivity, and the first and second source and drain layers have an n type conductivity.

15. A semiconductor device comprising: a semiconductor substrate;a first semiconductor region and a second semiconductor region formed on the semiconductor substrate to be insulated and separated from each other;a gate dielectric film formed on the semiconductor substrate to overlap the first semiconductor region and the second semiconductor region;a floating gate electrode which is formed on the gate dielectric film and in which a coupling capacitance with respect to the first semiconductor region is larger than a coupling capacitance with respect to the second semiconductor region;source and drain layers which are formed on a surface portion of the first semiconductor region to interpose the floating gate electrode therebetween;a first wiring line connected to one of the source and drain layers;a second wiring line connected to the other of the source and drain layers;a diffusion layer formed on a surface portion of the second semiconductor region including a part below the floating gate electrode; anda third wiring line connected to the diffusion layer.

16. The semiconductor device according to claim 15, wherein the first wiring line is a bit line, the second wiring line is a source line, and the third wiring line is a word line.

17. The semiconductor device according to claim 16, wherein the bit line and the source line are formed in the same layer, arranged above the word line and arranged in a direction perpendicular to the word line.

18. The semiconductor device according to claim 15, wherein the gate dielectric film has a thickness which is not smaller than 3.3 nm, and the semiconductor device functions as an electrically rewritable non-volatile semiconductor memory.

19. The semiconductor device according to claim 15, wherein the gate dielectric film has a thickness which is not greater than 3.3 nm, and the semiconductor device functions as an aging device which is turned on or off for a fixed time by storage of electric charge.

20. A semiconductor system constituted by connecting the plurality of semiconductor devices according to claim 19 in parallel or in series.

21. A semiconductor system constituted by connecting in series a series circuit in which the plurality of semiconductor devices according to claim 19 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and a parallel circuit in which the plurality of semiconductor devices according to claim 19 which are configured to be turned on for a fixed time by storage of electric charge are connected in parallel.

22. The semiconductor system according to claim 21, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is shorter than a time required for all the semiconductor devices included in the parallel circuit to be turned off.

23. A semiconductor system constituted by connecting in parallel a series circuit in which the plurality of semiconductor devices according to claim 19 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and the semiconductor device according to claim 19 which is configured to be turned on for a fixed time by storage of electric charge.

24. The semiconductor system according to claim 23, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is longer than a time required for the semiconductor device which is configured to be turned on for a fixed time by storage of electric charge to be turned off.

25. The semiconductor device according to claim 15, wherein an overlapping area of the floating gate electrode and the first semiconductor region is larger than an overlapping area of the floating gate electrode and the second semiconductor region.

26. The semiconductor device according to claim 15, wherein the floating gate electrode has a T-shape, and a gate width of the floating gate electrode on the first semiconductor side is longer than a gate width of the same on the second semiconductor region side.

27. The semiconductor device according to claim 15, wherein a dielectric constant of the gate dielectric film at a part on the first semiconductor region side is higher than that of the gate dielectric film at a part on the second semiconductor region side.

28. The semiconductor device according to claim 15, wherein the first semiconductor region and the second semiconductor region have a p type conductivity, and the diffusion layer has an n type conductivity.

29. A semiconductor device functioning as an aging device which is turned on or off for a fixed time by storage of electric charge, comprising: a semiconductor substrate;a first semiconductor region and a second semiconductor region formed on the semiconductor substrate to be insulated and separated from each other;a gate dielectric film with a thickness of 3.3 nm or below, which is formed on the semiconductor substrate to overlap the first semiconductor region and the second semiconductor region;a floating gate electrode which is formed on the gate dielectric film, formed into a T-shape in such a manner that a gate width thereof on the first semiconductor region side is longer than a gate width thereof on the second semiconductor region side, and formed in such a manner that a coupling capacitance thereof with respect to the first semiconductor region is larger than a coupling capacitance thereof with respect to the second semiconductor region;first source and drain layers which are formed on a surface of the first semiconductor region to interpose a part below the floating gate electrode therebetween, one of the first source and drain layers being connected to a bit line while the other of the same being connected to a source line; andsecond source and drain layers which are formed on a surface of the second semiconductor region to interpose a part below the floating gate electrode therebetween and connected to a word line in common.

30. A semiconductor system constituted by connecting the plurality of semiconductor devices according to claim 29 in parallel or in series.

31. A semiconductor system constituted by connecting in series a series circuit in which the plurality of semiconductor devices according to claim 29 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and a parallel circuit in which the plurality of semiconductor devices according to claim 29 which are configured to be turned on for a fixed time by storage of electric charge are connected in parallel.

32. The semiconductor system according to claim 31, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is shorter than a time required for all the semiconductor devices included in the parallel circuit to be turned off.

33. A semiconductor system constituted by connecting in parallel a series circuit in which the plurality of semiconductor devices according to claim 29 which are configured to be turned off for a fixed time by storage of electric charge are connected in series and the semiconductor device according to claim 29 which is configured to be turned on for a fixed time by storage of electric charge.

34. The semiconductor system according to claim 33, wherein a time required for all the semiconductor devices included in the series circuit to be turned on is longer than a time required for the semiconductor device which is configured to be turned on for a fixed time by storage of electric charge to be turned off.