SEMICONDUCTOR DEVICE COMPRISING A METALLIZATION LAYER STACK WITH A POROUS LOW-K MATERIAL HAVING AN ENHANCED INTEGRITY

Abstract

By using a patterned sacrificial layer for forming highly conductive metal regions, the formation of a reliable conductive barrier layer may be accomplished prior to the actual deposition of a low-k dielectric material. Hence, even highly porous dielectrics may be used in combination with highly conductive metals, substantially without compromising the diffusion characteristics and the electromigration performance. Hence, metallization layers for highly scaled semiconductor devices having critical dimensions of 50 nm and significantly less may be provided.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1j schematically illustrate cross-sectional views of a semiconductor device during the formation of a metallization layer including the low-k dielectric material according to illustrative embodiments of the present invention;

FIGS. 2 a-2f schematically depict cross-sectional views of a semiconductor device during the formation of a metallization layer for confining a highly conductive metal region prior to forming a low-k dielectric material, wherein a high degree of process compatibility with existing inlaid technology is maintained; and

FIGS. 3 a-3b schematically illustrate cross-sectional views of a semiconductor device during the formation of metal lines and vias in accordance with further illustrative embodiments of the present invention.

Claims

1. A method, comprising: forming an opening in a sacrificial layer formed above a substrate of a semiconductor device;forming a metal region in said opening;removing said sacrificial layer; anddepositing a low-k dielectric material to embed said metal region in said low-k dielectric material.

2. The method of claim 1, further comprising forming a conductive layer prior to forming said sacrificial layer, wherein said opening is formed to expose said conductive layer.

3. The method of claim 2, wherein said metal region covers a portion of said conductive layer, further comprising removing a non-covered portion of said conductive layer prior to depositing said low-k dielectric material.

4. The method of claim 3, wherein said conductive layer is removed by an electrochemical removal process.

5. The method of claim 4, wherein a material composition of said conductive layer is selected to have a higher removal rate compared to the material of said metal region.

6. The method of claim 2, wherein forming said conductive layer comprises forming a conductive barrier layer and a seed layer.

7. The method of claim 3, further comprising forming a conductive cover layer on exposed surfaces of said metal region after removing said non-covered portion of said conductive layer and prior to depositing said low-k dielectric material.

8. The method of claim 7, wherein said conductive cover layer is formed by an electrochemical deposition technique.

9. The method of claim 1, further comprising forming a conductive barrier layer after forming said opening and prior to forming said metal region.

10. The method of claim 9, wherein said conductive barrier layer is formed by at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and electroless plating.

11. The method of claim 9, further comprising forming a seed layer on said conductive barrier layer.

12. The method of claim 9, wherein said sacrificial layer is removed selectively to said metal region and said conductive barrier layer.

13. The method of claim 9, further comprising removing excess material of said low-k dielectric material to expose a top surface of said metal region.

14. The method of claim 13, further comprising forming a conductive capping layer on said exposed top surface.

15. The method of claim 14, wherein said conductive capping layer is formed by an electrochemical deposition technique.

16. The method of claim 1, wherein said opening is formed by lithography and etching.

17. The method of claim 1, wherein said opening is formed by an imprint technique.

18. A method, comprising: forming a metal region above a substrate of a semiconductor device, said metal region having a conductive barrier layer formed on at least a sidewall surface of said metal region; andforming a low-k dielectric layer on said previously formed conductive barrier layer.

19. The method of claim 18, wherein said metal comprises copper.

20. The method of claim 19, wherein forming said metal region comprises filling in a metal in an opening formed in a sacrificial layer, removing said sacrificial layer and forming said conductive barrier layer.

21. The method of claim 18, wherein forming said metal region comprises forming an opening in a sacrificial layer, forming said conductive barrier layer in said opening and filling said opening with a metal.

22. The method of claim 18, wherein said low-k dielectric layer is comprised of a porous material having a relative permittivity of approximately less than 3.0.